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| t he f ol l o w i ng do c um en t c o nta i ns i nf orm ati on o n c y pr es s produc ts .
mb9 152 0 series 32 - bit microcontroller fr family fr81s mb91f527r/u/m/y * , mb91f528r/u/m/y * data sheet ( full production ) publication number mb9 1 f 52 8_ ds70 5 - 000 16 revision 1. 0 issue date march 28 , 2014 confidential notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production ha s begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. d a t a s h e e t mb9 1 f 52 8_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential notice on data sheet designations sp a nsion inc. issues data sheets with advance information or preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full pr oduction. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and defini tions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information presented in a document with this designation is likely t o change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following conditions upon advance information content: this document contains information on one or more products under development at spansion inc . the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice. preliminary the prelimin ary designation indicates that the product development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subs equent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under consideration. spansion places the following conditions upon preliminary content: this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specification s. combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of document distinguishes these products and their designations wherever necessary, typically o n the first page, the ordering information page, and pages with the dc characteristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designa tion on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is removed from the data sheet. nominal changes may include those affecting the number of or dering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or vio range. changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. spansion inc. applies the following conditions to documents in this category: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient produc tion volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. questions regarding these document designations may b e directed to your local sales office. mb9 152 0 series 32 - bit microcontroller fr family fr81s mb91f527r/u/m/y * , mb91f528r/u/m/y * data sheet ( full production ) publication number mb9 1 f 52 8_ ds70 5 - 000 16 revision 1. 0 issue date march 28 , 2014 confidential this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been complete d, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. ? description the mb91520 series is a spansion 32 - bit microcontroller designed for automotive devices. this series contains the fr81s cpu which is compatible with the fr family. note : fr is a line of products of spans ion inc . *:this series is a composition of the kind that adds h c /j c /k c /l c /s c /u c /w c /y c to the end of the above - mentioned each name of articles of presence, according to presence of sub - clock, csv initial value and lvd initial value. please see " ordering i nformation" for details. spansion provides information facilitating product development via the following website. the website contains information useful for customers. http://www.spansion. com/support/microcontrollers/pages/default.aspx d a t a s h e e t 2 mb9 1 f 52 8_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? features ? fr81s cpu core ? 32 - bit risc, load/store architecture, 5 - stage pipeline ? maximum operating frequency: mb91f52xr/mb91f52xu (lqfp) : 80 mhz (source oscillation = 4.0 mhz and 20 multiplied (pll clock multiplication system)) mb91f52xr/mb91f52xu (teqfp) : 12 8 mhz (source oscillation = 4.0 mhz and 32 multiplied (pll clock multiplication system)) mb91f52xm/ mb91f52xy: 128 mhz (source oscillation = 4.0 mhz and 32 multiplied (pll clock multiplication system)) ? general - purpose register : 32 - bit 16 sets ? 16 - bit fixe d length instructions (basic instruction), 1 instruction per cycle ? instructions appropriate to embedded applications ? memory - to - memory transfer instruction ? bit processing instruction ? barrel shift instruction etc. ? high - level language support instructions ? fun ction entry/exit instructions ? register content multi - load and store instructions ? bit search instructions ? logical 1 detection, 0 detection, and change - point detection ? branch instructions with delay slot ? decrease overhead during branch process ? register inter lock function ? easy assembler writing ? built - in multiplier and instruction level support ? signed 32 - bit multiplication : 5 cycles ? signed 16 - bit multiplication : 3 cycles ? interrupt (pc/ps saving) ? 6 cycles (16 priority levels) ? the harvard architecture allows s imultaneous execution of program and data access. ? instruction compatibility with the fr family ? built - in memory protection function (mpu) ? eight protection areas can be specified commonly for instructions and the data. ? control access privilege in both privil ege mode and user mode. ? built - in fpu (floating point arithmetic) ? ieee754 compliant ? floating - point register 32 - bit 16 sets ? peripheral functions ? clock generation (equipped with sscg function) ? main oscillation (4mhz to 16mhz) ? sub oscillation (32khz) or no sub oscillation ? pll multiplication rate : 1 to 20 times for mb91f52xr/mb91f52xu (lqfp) : 1 to 32 times for mb91f52x r /mb91f52x u(teqfp) : 1 to 32 times for mb91f52xm /mb91f52xy ? 100 khz cr oscillator mounted ? maximum operating frequency: peripheral bus clock: 40 mhz external bus clock: 40mh z ? built - in program flash capacity mb91f52 7 : 1 536kb + 64kb mb91f528 : 2048kb + 64kb ? built - in data flash (workflash) 64kb d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 3 confidential ? built - in ram capacity ? main ram mb91f527 : 192kb mb91f528 : 192kb + 128kb (128 kb located in the ahb area, a penalty given at access ) ? backup ram 16 kb ? general - purpose ports : mb91f527r/mb91f528r : 115 (none sub oscillation), 113 (with sub oscillation) mb91f527u/mb91f528u : 147 (none sub oscillation), 145 (with sub oscillation) mb91f527m/mb91f528m : 177 (none su b oscillation), 175 (with sub oscillation) mb91f527y/MB91F528Y 219 (none sub oscillation), 217 (with sub oscillation) included i 2 c pseudo open drain ports : max. 30 ? external bus interface ? 22 - bit address, 8/ 16 - bit data ? dma controller ? up to 16 channels can b e started simultaneously. ? 2 transfer factors (internal peripheral request and software) ? a/d converter (successive approximation type) ? 12 - bit resolution : max. 64 channels (32 channels + 32 channels) ? conversion time : 1s ? d/a converter (r - 2r type) ? 8 - bit resolution : 2 channels ? external interrupt input: max. 24 channels ? level ("h" / "l"), or edge detection (rising or falling) supported ? multi - function serial communication (built - in transmission/receptio n fifo memory) : max. 20 channels 5v tolerant input 8 channels ( ch.6, ch.8, ch.9, ch.11 , ch.16 to ch.19 ) cmos hysteresis input < uart (asynchronous serial interface) > ? full - duplex double buffering system, 64 - byte transmission fifo memory, 64 - byte reception fifo memory ? parity or no parity is selectable. ? built - in dedicated baud rate generator ? the external clock can be used as the transfer clock ? parity, frame, and overrun error detect functions provided ? dma transfer support d a t a s h e e t 4 mb9 1 f 52 8_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential < i 2 c > ? 10 channels (ch.3 , ch. 4, ch.12 to ch.19 ) standard mode / h igh - speed mode supported ? 5 channels (ch.5 to ch. 8, ch.11) standard mode supported ? full - duplex double buffering system, 64 - byte transmission fifo memory, 64 - byte reception fifo memory ? standard mode (max. 100kbps) / h igh - speed mode (max. 400kbps) supported ? dma transfer supported (for transmission only) ? ca n : 6 channels ? transfer speed : up to 1mbps ? 128 - transmission/reception message buffering : 6 channel s ? flexray controller: 1 unit (ch.a/ch.b) ? flexray specification version 2.1 supported ? max. 128 - message buffer configuration ? 8 kb message ram ? variable - length m essage buffer configuration ? each message buffer can be configured as a part of a reception buffer, transmission buffer, or reception fifo. ? host access to message buffers through input and output buffers ? filtering the slot counter, cycle counter, and channe ls ? maskable interrupts ? ppg : 16 - bit max. 8 8 channels ? led drive output 4 channels (ch.11 to ch.14) ? reload timer : 16 - bit 8 channels ? free - run timer : 16 - bit 3 channels 32 - bit max. 8 channels ? input capture : 16 - bit 4 channels (linked to the free - run timer) 32 - bit max. 8 channels (linked to the free - run timer) ? output compare : 16 - bit 6 channels (linked to the free - run timer) 32 - bit max. 8 channels (linked to the free - run timer) ? wave generator : 6 channels ? u/d counter: ? 8/16 - bit up/down counter max. 4 channels ? real - time clock (rtc) (for day, hours, minutes, seconds) ? main oscillation / sub oscillation frequency can be selected for the operation clock . ? calibration: a real - time clock (rtc) of the sub clock drive. ? the main clock to sub clock ratio c an be corrected by setting the real - time clock prescaler ? clock supervisor ? monitoring abnormality (damage of crystal etc.) of sub oscillation (32 k hz) (dual clock products) and main oscillation (4 mhz). ? when abnormality is detecte d, it switches to the cr clo ck. ? for some devices , on/off can be selected as the initial value. ? base timer : 2 channels ? 16 - bit timer ? the timer mode is selected from pwm/ppg/pwc/reload. ? in the cascaded mode, a pair of 16 - bit timers can be used as one 32 - bit timer. ? crc generation ? watchd og timer ? hardware watchdog ? software watchdog (an effective range of a clear counter can be set.) ? nmi ? interrupt controller ? interrupt request batch read ? multiple interrupts from peripherals can be read by a series of registers . ? i/o relocation ? peripheral func tion pins can be reassigned. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 5 confidential ? low - power consumption mode ? sleep / stop / watch / sub run mode ? stop (power shutdown) / watch (power shutdown) mode ? power on reset ? low - voltage detection reset (external power supply and internal power supply are independently ob served.) ? for some devices, on/off can be selected as the initial value for external power supply. ? tuning ram ? capacity: 128 kb ? can be used as ram for data tuning. ? jtag pins (trst, tck, tms, tdi, tdo) ? device package : lqfp - 144/176/208, teqfp - 144 (planning) /17 6/208, bga - 416 ? cmos 90nm technology ? power supplies ? 5v or 3v power supply ? the internal 1.2v is generated from 5v with the voltage step - down regulator. ? restriction on the power - on sequence (from vcc to vcce) ? applying a voltage higher than the power supply vo ltage to an analog signal input is prohibited. ? operation guaranteed volta ge range (recommended): 3.0v to 5.5v (within the range guaranteed by ac and dc spec ) ? operation g uaranteed voltage range: 2.7v to 5.5 v d a t a s h e e t 6 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? product lineup ? product lineup comparison 14 4pin s mb91f52 7r mb91f52 8r system clock on - chip pll clock multiple method minimum instruction execution time 12.5ns(80mhz) (lqfp - 144) 8.0ns (128mhz) (teqfp - 144) flash capacity (program) 1536kb + 64kb 2048kb + 6 4kb flash capacity (data) 64kb ram capacity 192kb + 16kb (192kb + 128kb) + 16kb external bus i/f (22 address/16 data/4cs) yes dma transfer 16 channels 16 - bit base timer 2 channels free - run timer 16 - bit 3 channels 32 - bit 3 channels input capture 16 - bit 4 channels 32 - bit 6 channels output compare 16 - bit 6 channels 32 - bit 6 channels 16 - bit reload timer 8 channels ppg 16 - bit 44 channels * 2 up/down counter 2 channels clock supervisor yes external interrupt 8 channels 2 units a/d 12 - bit 32 channels (1 unit) 12 - bit 16 channels (1 unit) d/a (8 - bit) 2 channels multi - function serial 12 channels can 128msg 6 channels flexray 1 channel hardware watchdog yes crc generation yes d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 7 confidential mb91f52 7r mb91f52 8r low - voltage detection reset yes flash security yes ecc flash/workflash yes ecc ram yes memory protection function (mpu) yes floating - point arithmetic (fpu) yes real time clock (rtc) yes general - purpose port (#gpios) 115 ports (no sub clock) / 113 ports (with sub clock) sscg yes sub clock yes cr os cillator yes nmi request function yes ocd(on chip debug) yes tpu (timing protection unit) yes key code register yes wave generator 6 channels tuning ram none yes jtag yes operation guaranteed temperature (ta) - 40c to +125 c * 1 power supply 2.7 v to 5.5 v vcce = 5.0 v10% or vcce = 3.0 v to 3.6 v (vcce: 1 - pin to 39 - pin and 128 - pin to 144 - pin power supply) (external bus i/f: 3.0 v to 3.6 v) package lqfp - 144 / teqfp - 144 (planning) * 3 * 1 : the limitation with the package has been described by the it em of the power consumption of "absolute maximum rating s ". * 2 : ppg output pins on ch.38 and ch.39 do not exist. see " pins of ppg (ch.0 to ch.87)." * 3 : teqfp - 144pin is planning. please contact sales representatives about details. d a t a s h e e t 8 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? product lineup comparison 176 p in s mb91f52 7u mb91f52 8u system clock on - chip pll clock multiple method minimum instruction execution time 12.5ns(80mhz) (lqfp - 176) 8.0ns(128mhz) (teqfp - 176) flash capacity (program) 1536kb + 64kb 2048kb + 64kb flash capacity (data) 64kb ram cap acity 192kb + 16kb (192kb + 128kb) + 16kb external bus i/f (22 address/16 data/4cs) yes dma transfer 16 channels 16 - bit base timer 2 channels free - run timer 16 - bit 3 channels 32 - bit 3 channels input capture 16 - bit 4 channels 32 - bit 6 channels output compare 16 - bit 6 channels 32 - bit 6 channels 16 - bit reload timer 8 channels ppg 16 - bit 48 channels up/down counter 2 channels clock supervisor yes external interrupt 8 channels 2 units a/d 12 - bit 32 channels (1 unit) 12 - bit 16 chan nels (1 unit) d/a (8 - bit) 2 channels multi - function serial 12 channels can 128msg 6 channels flexray 1 channel hardware watchdog yes crc generation yes low - voltage detection reset yes d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 9 confidential mb91f52 7u mb91f52 8u flash security yes ecc flash/workflash yes ecc ram yes memo ry protection function (mpu) yes floating - point arithmetic (fpu) yes real time clock (rtc) yes general - purpose port (#gpios) 147 ports (no sub clock) / 145 ports (with sub clock) sscg yes sub clock yes cr oscillator yes nmi request function yes ocd (on chip debug) yes tpu (timing protection unit) yes key code register yes wave generator 6 channels tuning ram none yes jtag yes operation guaranteed temperature (ta) - 40c to +125 c * 1 power supply 2.7 v to 5.5 v vcce = 5.0 v10% or vcce = 3.0 v to 3.6 v (vcce: 1 - pin to 49 - pin and 156 - pin to 176 - pin power supply) (external bus i/f: 3.0 v to 3.6 v) package lqfp - 176 / teqfp - 176 * 1 : the limitation with the package has been described by the item of the power consumption of "absolute maximum rating s ". d a t a s h e e t 10 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? product lineup comparison 208 p in s mb91f52 7m mb91f52 8m system clock on - chip pll clock multiple method minimum instruction execution time 8.0ns (128mhz) flash capacity (program) 1536kb + 64kb 2048kb + 64kb flash capacity (data) 64kb ram capacity 192kb + 16kb (192kb + 128kb) + 16kb external bus i/f (22 address/16 data/4cs) yes dma transfer 16 channels 16 - bit base timer 2 channels free - run timer 16 - bit 3 channels 32 - bit 8 channels input capture 16 - bit 4 channels 32 - bit 8 channels outpu t compare 16 - bit 6 channels 32 - bit 8 channels 16 - bit reload timer 8 channels ppg 16 - bit 64 channels up/down counter 4 channels clock supervisor yes external interrupt 8 channels 3 units a/d 12 - bit 32 channels (2 units) d/a (8 - bit) 2 channe ls multi - function serial 20 channels can 128msg 6 channels flexray 1 channel hardware watchdog yes crc generation yes low - voltage detection reset yes flash security yes d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 11 confidential mb91f52 7m mb91f52 8m ecc flash/workflash yes ecc ram yes memory protection function (mpu) yes f loating - point arithmetic (fpu) yes real time clock (rtc) yes general - purpose port (#gpios) 177 ports (no sub clock) / 175 ports (with sub clock) sscg yes sub clock yes cr oscillator yes nmi request function yes ocd(on chip debug) yes tpu (timing p rotection unit) yes key code register yes wave generator 6 channels tuning ram none yes jtag yes operation guaranteed temperature (ta) - 40c to +125 c * 1 power supply 2.7 v to 5.5 v vcce = 5.0 v10% or vcce = 3.0 v to 3.6 v (vcce: 1 - pin to 57 - pin and 188 - pin to 208 - pin power supply) (external bus i/f: 3.0 v to 3.6 v) package lqfp - 208 / teqfp - 208 * 1 : the limitation with the package has been described by the item of the power consumption of "absolute maximum rating s ". d a t a s h e e t 12 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? product lineup comparison 416 p in s mb91f52 7y mb91f52 8y system clock on - chip pll clock multiple method minimum instruction execution time 8.0ns (128mhz) flash capacity (program) 1536kb + 64kb 2048kb + 64kb flash capacity (data) 64kb ram capacity 192kb + 16kb (192kb + 128kb) + 16kb external bus i/f (22 address/16 data/4cs) yes dma transfer 16 channels 16 - bit base timer 2 channels free - run timer 16 - bit 3 channels 32 - bit 8 channels input capture 16 - bit 4 channels 32 - bit 8 channels output compare 16 - bit 6 channels 32 - bi t 8 channels 16 - bit reload timer 8 channels ppg 16 - bit 88 channels up/down counter 4 channels clock supervisor yes external interrupt 8 channels 3 units a/d 12 - bit 32 channels (2 units) d/a (8 - bit) 2 channels multi - function serial 20 channe ls can 128msg 6 channels flexray 1 channel hardware watchdog yes crc generation yes low - voltage detection reset yes flash security yes d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 13 confidential mb91f52 7y mb91f52 8y ecc flash/workflash yes ecc ram yes memory protection function (mpu) yes floating - point arithmetic (fpu) yes real time clock (rtc) yes general - purpose port (#gpios) 219 ports (no sub clock) / 217 ports (with sub clock) sscg yes sub clock yes cr oscillator yes nmi request function yes ocd(on chip debug) yes tpu (timing protection unit) yes key code regis ter yes wave generator 6 channels tuning ram none yes jtag yes operation guaranteed temperature (ta) - 40c to +125 c power supply 2.7 v to 5.5 v vcce = 5.0 v10% or vcce = 3.0 v to 3.6 v (vcce: see pin assignment) (external bus i/f: 3.0 v to 3.6 v) p ackage bga - 416 d a t a s h e e t 14 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? table for clock supervisor and external low voltage detection reset initial value on/off clock initial value of clock supervisor initial value of external low - voltage detection reset function single on on s off u off on h off k dual on on w off y off on j off l mb91f52xxyz revision: c function: see table 3 - 5 pkg type: r 144 pin u 176 pin m 208 pin y bga 416 pin memory size: 7 1.5mb 8 2mb d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 15 confidential ? pin assignment ? mb91f52x r mb91f52 7r , mb91f52 8r (top view) vcce p014/d28/tiob1_0 p013/d27/tioa1_0 p012/d26/tiob0_0/stopwt_0 p011/wot/d25/sot2_1/tioa0_0/int3_1 p010/d24/rxdb_0 p007/d23/txdb_0 p006/d22/scs2_0/adtg1_1/int2_1/txenb_0 p005/d21/sck2_0/adtg0_1/int7_1/rxda_0 p004/d20/sot2_0/txda_0 p003/d19/sin2_0/tiob1_1/int3_0/txena_0 p002/d18/sck1_0/tiob0_1 p001/d17/sot1_0/tioa1_1 p000/d16/sin1_0/tioa0_1/int2_0 c vss vcce p134/rx2(128)_0/scs1_1/icu7_0/int7_0 p133/tx2(128)_0 vss vcc rstx x0a/p136 x1a/p135/dtti_0 vss x1 x0 md1 md0 p130/sck0_0/tck p127/sot0_0/tdo p126/sin0_0/int6_0/tdi p125/ocu11_0/tms p124/ocu10_0/trst debugif vcc 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vss 1 108 vss p015/d29/trg0_0 2 107 p123/ocu9_0/stopwt_1 p016/d30/trg1_0 3 106 p122/sin6_0/an31/ocu8_0/int9_1 p017/d31/trg2_0 4 105 p121/ocu7_0/ppg23_0/tx4(128)_0 p020/asx/sin3_1/trg3_0/tin0_2/rto5_1 5 104 p120/an30/ocu6_0/ppg22_0/int9_0/rx4(128)_0 p021/cs0x/sot3_1/trg6_1/trg4_0 6 103 p117/scs60_0/an29/ppg21_0/rto5_0 p022/cs1x/sck3_1/trg7_1/trg5_0 7 102 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p023/rdx/scs3_1/ppg32_0/tin0_0 8 101 p115/rx1(128)_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p024/wr0x/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 9 100 p114/scs61_0/an26/ppg18_0/rto2_0/rxdb_1 p025/wr1x/sot4_1/ppg25_0/tin2_0 10 99 p113/an25/ppg17_0/rto1_0/txdb_1 p026/a00/sck4_1/ppg26_0/tin3_0 11 98 p112/an24/ppg16_0/rto0_0/txenb_1 p027/a01/scs40_1/ppg27_0/tot0_0/rto3_1 12 97 p111/rx1(128)_0/scs62_0/an23/int1_0 p030/a02/scs41_1/ppg28_0/tot1_0 13 96 p110/tx1(128)_0/scs63_0/an22 p031/a03/scs42_1/ppg29_0/tot2_0 14 95 nmix p032/a04/scs43_1/ppg30_0/tot3_0/rto2_1 15 94 p155/an21/rxda_1 p033/a05/ppg31_0/icu3_3/tin4_0/rto1_1/sck3_2 16 93 p154/an20/txda_1 p034/a06/ocu11_1/icu2_3/tin5_0/rto0_1/sot3_2 17 92 p107/an19/ppg15_0/txena_1 p150/sot8_0/sda8/ocu10_1/trg6_0/icu1_3/tin6_0/rdy_1 18 91 p106/scs70_0/an18/ppg14_0 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 19 90 p105/scs71_0/an17/ppg13_0 p035/a07/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 20 89 p104/scs72_0/an16/ppg12_0 p036/a08/scs8_0/ocu7_1/tot5_0/bin0_0 21 88 p103/scs73_0/an15/ppg11_0 p037/a09/ocu6_1/tot6_0/zin0_0 22 87 p102/sin7_0/an14/ppg10_0/int10_0/rx3(128)_0 p040/a10/ppg23_1/tot7_0/ain1_0/sin0_1 23 86 p101/sot7_0/sda7/an13/ppg9_0/tx3(128)_0 p041/a11/sin9_0/icu9_1/bin1_0/int12_0 24 85 p100/sck7_0/scl7/an12/ppg8_0 p042/a12/sot9_0/an47/icu8_1/trg0_1/zin1_0 25 84 avcc0 p043/a13/icu7_1/trg1_1 26 83 avrh0 p044/a14/scs9_0/icu6_1/trg2_1 27 82 avss0/avrl0 p045/a15/sck9_0/an46/icu5_1/trg3_1/tot1_2 28 81 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p046/a16/icu4_1/trg4_1 29 80 p096/rx0(128)_0/sot11_0/sda11/an10/int0_0 p047/a17/an45/trg8_0/tin3_2/sot0_1 30 79 p095/tx0(128)_0/scs11_0/an9 p050/a18/trg5_1/ppg33_0 31 78 p094/an8/icu4_0/tot3_1 p051/a19/trg9_0/tx5(128)_0 32 77 p093/tx0(128)_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 p052/a20/ppg34_0/int14_0/rx5(128)_0 33 76 p092/an6/ppg40_1/icu2_0/tot0_1 p053/a21/an44/ppg35_0/int14_1/sck0_1 34 75 p091/an5/ppg41_1/icu1_0/tin3_1 p054/sysclk/ppg36_0 35 74 p090/an4/icu0_0/tin2_1 vcce 36 73 vss 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vss p055/cs2x/sin10_0/an43/ppg37_0/tin4_1 p056/cs3x/icu9_0/ppg0_1/icu0_1/tin5_1/dtti_2 avcc1 p057/rdy_0/sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 vss vcc p060/scs10_0/ppg2_1/icu2_1/tot5_1/int13_0 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p063/scs41_0/an39/ppg5_1/frck1_0/bin1_1 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p065/scs43_0/frck3_0/zin0_1/ppg44_1 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p067/an36/frck5_0/ain0_1 p070/icu0_2 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p073/sot4_0/sda4/an33/icu3_2 p074/sck4_0/scl4 p075/sin3_0/int4_0/rx5(128)_1 p076/sot3_0/sda3/tx5(128)_1 p077/sck3_0/scl3 p152/scs53_0 p153/sck5_0/scl5/an32/frck1_1/int4_1 p080/scs52_0/ppg0_0 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p083/scs50_0/an2/ppg3_0 p084/scs51_0/an3/ppg4_0 p085/ppg5_0 p086/dao1/ppg6_0 p087/dao0/ppg7_0/int8_0 vcc top view lqfp-144 teqfp-144 power supply gr.2 power supply gr.1 d a t a s h e e t 16 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? mb91f52x u mb91f52 7u , mb91f52 8u (top view) vcce p014/d28/tiob1_0 p013/d27/tioa1_0 p167/ppg35_1 p012/d26/tiob0_0/stopwt_0 p011/wot/d25/sot2_1/tioa0_0/int3_1 p010/d24/rxdb_0 p166/ppg34_1 p007/d23/txdb_0 p006/d22/scs2_0/adtg1_1/int2_1/txenb_0 p165/ppg33_1 p005/d21/sck2_0/adtg0_1/int7_1/rxda_0 p164/ppg32_1 p004/d20/sot2_0/txda_0 p003/d19/sin2_0/tiob1_1/int3_0/txena_0 p002/d18/sck1_0/tiob0_1 p001/d17/sot1_0/tioa1_1 p000/d16/sin1_0/tioa0_1/int2_0 c vss vcce p134/rx2(128)_0/scs1_1/icu7_0/int7_0 p133/tx2(128)_0 vss vcc rstx x0a/p136 x1a/p135/dtti_0 vss x1 x0 md1 md0 p163/trg6_2 p162/trg5_2 p130/sck0_0/tck p127/sot0_0/tdo p126/sin0_0/int6_0/tdi p125/ocu11_0/tms p124/ocu10_0/trst p161/ppg31_1 p160/ppg30_1 debugif vcc 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 vss 1 132 vss p015/d29/trg0_0 2 131 p123/ocu9_0/stopwt_1 p016/d30/trg1_0 3 130 p197/ppg29_1 p170/ppg36_1 4 129 p122/sin6_0/an31/ocu8_0/int9_1 p017/d31/trg2_0 5 128 p121/ocu7_0/ppg23_0/tx4(128)_0 p171/ppg37_1 6 127 p120/an30/ocu6_0/ppg22_0/int9_0/rx4(128)_0 p020/asx/sin3_1/trg3_0/tin0_2/rto5_1 7 126 p196/frck3_1/ppg28_1 p021/cs0x/sot3_1/trg6_1/trg4_0 8 125 p117/scs60_0/an29/ppg21_0/rto5_0 p022/cs1x/sck3_1/trg7_1/trg5_0 9 124 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p023/rdx/scs3_1/ppg32_0/tin0_0 10 123 p115/rx1(128)_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p024/wr0x/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 11 122 p114/scs61_0/an26/ppg18_0/rto2_0/rxdb_1 p025/wr1x/sot4_1/ppg25_0/tin2_0 12 121 p195/frck4_1/ppg27_1 p172/ppg38_1 13 120 p194/frck5_1/ppg26_1 p026/a00/sck4_1/ppg26_0/tin3_0 14 119 p113/an25/ppg17_0/rto1_0/txdb_1 p027/a01/scs40_1/ppg27_0/tot0_0/rto3_1 15 118 p112/an24/ppg16_0/rto0_0/txenb_1 p173/ppg39_1 16 117 p111/rx1(128)_0/scs62_0/an23/int1_0 p030/a02/scs41_1/ppg28_0/tot1_0 17 116 p110/tx1(128)_0/scs63_0/an22 p031/a03/scs42_1/ppg29_0/tot2_0 18 115 nmix p032/a04/scs43_1/ppg30_0/tot3_0/rto2_1 19 114 p155/an21/rxda_1 p033/a05/ppg31_0/icu3_3/tin4_0/rto1_1/sck3_2 20 113 p154/an20/txda_1 p034/a06/ocu11_1/icu2_3/tin5_0/rto0_1/sot3_2 21 112 p193/ppg25_1 p150/sot8_0/sda8/ocu10_1/trg6_0/icu1_3/tin6_0/rdy_1 22 111 p107/an19/ppg15_0/txena_1 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 23 110 p106/scs70_0/an18/ppg14_0 p035/a07/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 24 109 p105/scs71_0/an17/ppg13_0 p036/a08/scs8_0/ocu7_1/tot5_0/bin0_0 25 108 p104/scs72_0/an16/ppg12_0 p037/a09/ocu6_1/tot6_0/zin0_0 26 107 p103/scs73_0/an15/ppg11_0 p174/trg8_1 27 106 p102/sin7_0/an14/ppg10_0/int10_0/rx3(128)_0 p175/trg9_1 28 105 p101/sot7_0/sda7/an13/ppg9_0/tx3(128)_0 p040/a10/ppg23_1/tot7_0/ain1_0/sin0_1 29 104 p100/sck7_0/scl7/an12/ppg8_0 p041/a11/sin9_0/icu9_1/bin1_0/int12_0 30 103 avcc0 p042/a12/sot9_0/an47/icu8_1/trg0_1/zin1_0 31 102 avrh0 p043/a13/icu7_1/trg1_1 32 101 avss0/avrl0 p044/a14/scs9_0/icu6_1/trg2_1 33 100 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p045/a15/sck9_0/an46/icu5_1/trg3_1/tot1_2 34 99 p096/rx0(128)_0/sot11_0/sda11/an10/int0_0 p046/a16/icu4_1/trg4_1 35 98 p095/tx0(128)_0/scs11_0/an9 p176/trg10_0 36 97 p094/an8/icu4_0/tot3_1 p047/a17/an45/trg8_0/tin3_2/sot0_1 37 96 p093/tx0(128)_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 p177/trg11_0 38 95 p192/ppg24_1/tot1_1 p050/a18/trg5_1/ppg33_0 39 94 p092/an6/ppg40_1/icu2_0/tot0_1 p051/a19/trg9_0/tx5(128)_0 40 93 p091/an5/ppg41_1/icu1_0/tin3_1 p052/a20/ppg34_0/int14_0/rx5(128)_0 41 92 p090/an4/icu0_0/tin2_1 p053/a21/an44/ppg35_0/int14_1/sck0_1 42 91 p191/tin1_1 p054/sysclk/ppg36_0 43 90 p190/tin0_1 vcce 44 89 vss 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 vss p055/cs2x/sin10_0/an43/ppg37_0/tin4_1 p180/ppg40_0 p181/ppg41_0 p056/cs3x/icu9_0/ppg0_1/icu0_1/tin5_1/dtti_2 avcc1 p057/rdy_0/sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 vss vcc p182/ppg42_0 p060/scs10_0/ppg2_1/icu2_1/tot5_1/int13_0 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p063/scs41_0/an39/ppg5_1/frck1_0/bin1_1 p183/ppg43_0 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p065/scs43_0/frck3_0/zin0_1/ppg44_1 p184/ppg44_0 p185/ppg45_0 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p067/an36/frck5_0/ain0_1 p070/icu0_2 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p073/sot4_0/sda4/an33/icu3_2 p186/ppg46_0 p187/ppg47_0 p074/sck4_0/scl4 p075/sin3_0/int4_0/rx5(128)_1 p076/sot3_0/sda3/tx5(128)_1 p077/sck3_0/scl3 p152/scs53_0 p153/sck5_0/scl5/an32/frck1_1/int4_1 p080/scs52_0/ppg0_0 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p083/scs50_0/an2/ppg3_0 p084/scs51_0/an3/ppg4_0 p085/ppg5_0 p086/dao1/ppg6_0 p087/dao0/ppg7_0/int8_0 vcc top view lqfp-176 teqfp-176 power supply gr.2 power supply gr.1 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 17 confidential ? mb91f52x m mb91f52 7m , mb91f52 8m (top view) vcce p014/d28/tiob1_0 p013/d27/tioa1_0 p167/ppg35_1 p012/d26/tiob0_0/stopwt_0 p011/wot/d25/sot2_1/tioa0_0/int3_1 p237/scs19_0/trg15_0/zin3_0 p236/sin19_0/trg14_0/bin3_0/int23_0 p235/sot19_0/sda19/ppg63_0/ain3_0 p234/sck19_0/scl19/ppg62_0 p010/d24/rxdb_0 p166/ppg34_1 p007/d23/txdb_0 p006/d22/scs2_0/adtg1_1/int2_1/txenb_0 p165/ppg33_1 p005/d21/sck2_0/adtg0_1/int7_1/rxda_0 p164/ppg32_1 p004/d20/sot2_0/txda_0 p003/d19/sin2_0/tiob1_1/int3_0/txena_0 p002/d18/sck1_0/tiob0_1 p001/d17/sot1_0/tioa1_1 p000/d16/sin1_0/tioa0_1/int2_0 c vss vcce p134/rx2(128)_0/scs1_1/icu7_0/int7_0 p133/tx2(128)_0 vss vcc rstx x0a/p136 x1a/p135/dtti_0 vss x1 x0 md1 md0 p163/trg6_2 p162/trg5_2 p130/sck0_0/tck p127/sot0_0/tdo p126/sin0_0/int6_0/tdi p233/scs18_0/ppg61_0/int16_1 p232/sin18_0/ppg60_0/int22_0 p231/sot18_0/sda18/ocu13_0/ppg59_0 p230/sck18_0/scl18/ocu12_0/ppg58_0 p125/ocu11_0/tms p124/ocu10_0/trst p161/ppg31_1 p160/ppg30_1 debugif vcc 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 vss 1 156 vss p015/d29/trg0_0 2 155 p123/ocu9_0/stopwt_1 p016/d30/trg1_0 3 154 p197/ppg29_1 p170/ppg36_1 4 153 p227/sin17_0/ppg57_0/int21_0 p017/d31/trg2_0 5 152 p226/sot17_0/sda17/ppg56_0 p171/ppg37_1 6 151 p225/sck17_0/scl17/ppg55_0 p020/asx/sin3_1/trg3_0/tin0_2/rto5_1 7 150 p122/sin6_0/an31/ocu8_0/int9_1 p021/cs0x/sot3_1/trg6_1/trg4_0 8 149 p121/ocu7_0/ppg23_0/tx4(128)_0 p022/cs1x/sck3_1/trg7_1/trg5_0 9 148 p120/an30/ocu6_0/ppg22_0/int9_0/rx4(128)_0 p023/rdx/scs3_1/ppg32_0/tin0_0 10 147 p196/frck3_1/ppg28_1 p024/wr0x/sin4_1/ppg24_0/tin1_0/rto4_1/int15_0 11 146 p117/scs60_0/an29/ppg21_0/rto5_0 p025/wr1x/sot4_1/ppg25_0/tin2_0 12 145 p116/sck6_0/scl6/an28/ppg20_0/rto4_0 p172/ppg38_1 13 144 p115/rx1(128)_1/sot6_0/sda6/an27/ppg19_0/rto3_0/int1_1 p026/a00/sck4_1/ppg26_0/tin3_0 14 143 p114/scs61_0/an26/ppg18_0/rto2_0/rxdb_1 p027/a01/scs40_1/ppg27_0/tot0_0/rto3_1 15 142 p195/frck4_1/ppg27_1 p173/ppg39_1 16 141 p194/frck5_1/ppg26_1 p030/a02/scs41_1/ppg28_0/tot1_0 17 140 p113/an25/ppg17_0/rto1_0/txdb_1 p031/a03/scs42_1/ppg29_0/tot2_0 18 139 p112/an24/ppg16_0/rto0_0/txenb_1 p032/a04/scs43_1/ppg30_0/tot3_0/rto2_1 19 138 p111/rx1(128)_0/scs62_0/an23/int1_0 p200/sck12_0/scl12/an63/trg12_0 20 137 p110/tx1(128)_0/scs63_0/an22 p201/sot12_0/sda12/an62/trg13_0 21 136 nmix p202/sin12_0/an61/int16_0 22 135 vss p203/scs12_0/an60 23 134 vcc p033/a05/ppg31_0/icu3_3/tin4_0/rto1_1/sck3_2 24 133 p155/an21/rxda_1 p034/a06/ocu11_1/icu2_3/tin5_0/rto0_1/sot3_2 25 132 p154/an20/txda_1 p150/sot8_0/sda8/ocu10_1/trg6_0/icu1_3/tin6_0/rdy_1 26 131 p193/ppg25_1 p151/sck8_0/scl8/ocu9_1/trg7_0/icu0_3/tin7_0/zin0_2/dtti_1 27 130 p107/an19/ppg15_0/txena_1 p035/a07/sin8_0/ocu8_1/tot4_0/ain0_0/int11_0 28 129 p106/scs70_0/an18/ppg14_0 p036/a08/scs8_0/ocu7_1/tot5_0/bin0_0 29 128 p105/scs71_0/an17/ppg13_0 p037/a09/ocu6_1/tot6_0/zin0_0 30 127 p104/scs72_0/an16/ppg12_0 p174/trg8_1 31 126 p103/scs73_0/an15/ppg11_0 p175/trg9_1 32 125 p102/sin7_0/an14/ppg10_0/int10_0/rx3(128)_0 p040/a10/ppg23_1/tot7_0/ain1_0/sin0_1 33 124 p101/sot7_0/sda7/an13/ppg9_0/tx3(128)_0 p041/a11/sin9_0/icu9_1/bin1_0/int12_0 34 123 p100/sck7_0/scl7/an12/ppg8_0 p042/a12/sot9_0/an47/icu8_1/trg0_1/zin1_0 35 122 avcc0 p043/a13/icu7_1/trg1_1 36 121 avrh0 p044/a14/scs9_0/icu6_1/trg2_1 37 120 avss0/avrl0 p045/a15/sck9_0/an46/icu5_1/trg3_1/tot1_2 38 119 p222/sin16_0/ppg54_0/int20_0 p204/sck13_0/scl13/an59/ppg48_0 39 118 p221/sot16_0/sda16/icu11_0/ppg49_1 p205/sot13_0/sda13/an58/ppg49_0/ain2_0 40 117 p220/sck16_0/scl16/icu10_0/ppg48_1 p206/sin13_0/an57/bin2_0/int17_0 41 116 p097/sck11_0/scl11/an11/icu5_0/ppg17_1 p207/scs13_0/an56/zin2_0 42 115 p096/rx0(128)_0/sot11_0/sda11/an10/int0_0 p046/a16/icu4_1/trg4_1 43 114 p095/tx0(128)_0/scs11_0/an9 p176/trg10_0 44 113 p094/an8/icu4_0/tot3_1 p047/a17/an45/trg8_0/tin3_2/sot0_1 45 112 p093/tx0(128)_1/sin11_0/an7/icu4_2/ppg16_1/icu3_0/tot2_1 p177/trg11_0 46 111 p192/ppg24_1/tot1_1 p050/a18/trg5_1/ppg33_0 47 110 p092/an6/ppg40_1/icu2_0/tot0_1 p051/a19/trg9_0/tx5(128)_0 48 109 p091/an5/ppg41_1/icu1_0/tin3_1 p052/a20/ppg34_0/int14_0/rx5(128)_0 49 108 p090/an4/icu0_0/tin2_1 p053/a21/an44/ppg35_0/int14_1/sck0_1 50 107 p191/tin1_1 p054/sysclk/ppg36_0 51 106 p190/tin0_1 vcce 52 105 vss 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 vss p055/cs2x/sin10_0/an43/ppg37_0/tin4_1 p180/ppg40_0 p181/ppg41_0 p056/cs3x/icu9_0/ppg0_1/icu0_1/tin5_1/dtti_2 avcc1 p057/ rdy_0 /sck10_1/an42/icu8_0/trg0_2/ppg1_1/icu1_1/tin6_1 avrh1 avss1/avrl1 vss vcc p182/ppg42_0 p210/sck14_0/scl14/an55/ppg50_0/ain2_1 p211/sot14_0/sda14/an54/ppg51_0/bin2_1 p212/sin14_0/an53/frck6_0/zin2_1/int18_0 p213/scs14_0/an52/frck7_0/int17_1 p060/scs10_0/ppg2_1/icu2_1/tot5_1/int13_0 p061/sot10_1/an41/icu6_0/ppg3_1/icu3_1/tot6_1/int13_1 p062/scs10_1/scs40_0/an40/ppg4_1/frck0_0/tot7_1/zin1_1 p063/scs41_0/an39/ppg5_1/frck1_0/bin1_1 p183/ppg43_0 p064/scs42_0/an38/frck2_0/ain1_1/ppg43_1 p065/scs43_0/frck3_0/zin0_1/ppg44_1 p184/ppg44_0 p185/ppg45_0 p066/sot4_2/scs3_0/an37/frck4_0/bin0_1 p067/an36/frck5_0/ain0_1 p070/icu0_2 p071/sck4_2/an35/icu1_2/monclk p072/sin4_0/an34/icu2_2/int5_0 p073/sot4_0/sda4/an33/icu3_2 p186/ppg46_0 p187/ppg47_0 p074/sck4_0/scl4 p214/sck15_0/scl15/an51/ppg52_0 p215/sot15_0/sda15/an50/frck8_0/ppg53_0 p216/sin15_0/an49/frck9_0/trg12_1/int19_0 p217/scs15_0/an48/frck10_0/trg13_1 p075/sin3_0/int4_0/rx5(128)_1 p076/sot3_0/sda3/tx5(128)_1 p077/sck3_0/scl3 p152/scs53_0 p153/sck5_0/scl5/an32/frck1_1/int4_1 p080/scs52_0/ppg0_0 p081/sot5_0/sda5/an0/ppg1_0 p082/sin5_0/an1/ppg2_0 p083/scs50_0/an2/ppg3_0 p084/scs51_0/an3/ppg4_0 p085/ppg5_0 p086/dao1/ppg6_0 p087/dao0/ppg7_0/int8_0 vcc top view lqfp-208 teqfp-208 power supply gr.2 power supply gr.1 d a t a s h e e t 18 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? mb91f52x y mb91f52 7y , mb91f52 8y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a vss b 1 vss b 100 vcce b 99 p014 b 98 p012 b 97 p010 b 96 p006 b 95 p004 b 94 p002 b 93 p000 b 92 vcce b 91 vss b 90 c b 89 vcc b 88 vss b 87 p136 b 86 p135 b 85 vss b 84 x1 b 83 x0 b 82 vss b 81 p125 b 80 md1 b 79 vcc b 78 vss b 77 vss b 76 a b vss b 2 vss b 101 vcce b 192 vss b 191 p013 b 190 p011 b 189 p007 b 188 p005 b 187 p003 b 186 p001 b 185 vcce b 184 vss b 183 vss b 182 vcc b 181 rstx b 180 vss b 179 vss b 178 p291 b 177 vss b 176 vss b 175 p230 b 174 p286 b 173 md0 b 172 vcc b 171 vss b 170 vss b 75 b c p015 b 3 vss b 102 vss b 193 p296 b 276 p295 b 275 p294 b 274 vss b 273 vss b 272 p234 b 271 p293 b 270 p165 b 269 vss b 268 vss b 267 vss b 266 vss b 265 p162 b 264 p127 b 263 p126 b 262 p233 b 261 p231 b 260 p287 b 259 p160 b 258 vss b 257 vss b 256 p284 b 169 debugif b 74 c d p016 b 4 p017 b 103 p240 b 194 vss b 277 p297 b 352 p167 b 351 p237 b 350 p236 b 349 p235 b 348 p166 b 347 p292 b 346 p164 b 345 vss b 344 p134 b 343 p133 b 342 p163 b 341 p130 b 340 p290 b 339 p232 b 338 p124 b 337 p161 b 336 p285 b 335 vss b 334 vss b 255 p226 b 168 p121 b 73 d e p020 b 5 p021 b 104 p170 b 195 p241 b 278 index p123 b 333 p227 b 254 p122 b 167 p282 b 72 e f p022 b 6 p023 b 105 vss b 196 p171 b 279 power supply gr.2 power supply gr.1 p197 b 332 vss b 253 p283 b 166 p115 b 71 f g p024 b 7 p025 b 106 vss b 197 p242 b 280 p225 b 331 vss b 252 p116 b 165 p280 b 70 g h p026 b 8 vss b 107 vss b 198 p243 b 281 p120 b 330 p117 b 251 p281 b 164 p194 b 69 h j p027 b 9 p030 b 108 p244 b 199 p245 b 282 p196 b 329 vss b 250 p195 b 163 p111 b 68 j k p031 b 10 p032 b 109 p172 b 200 p173 b 283 vss b 353 vss b 380 vss b 379 vss b 378 vss b 377 vss b 376 vss b 375 vss b 374 p114 b 328 vss b 249 p113 b 162 p112 b 67 k l p033 b 11 p034 b 110 p200 b 201 p201 b 284 vss b 354 vss b 381 vss b 400 vss b 399 vss b 398 vss b 397 vss b 396 vss b 373 p110 b 327 p277 b 248 nmix b 161 p155 b 66 l m vcce b 12 vcce b 111 p202 b 202 p203 b 285 vss b 355 vss b 382 vss b 401 vss b 412 vss b 411 vss b 410 vss b 395 vss b 372 vss b 326 vss b 247 vss b 160 vss b 65 m n vss b 13 vss b 112 vss b 203 vss b 286 vss b 356 vss b 383 vss b 402 vss b 413 vss b 416 vss b 409 vss b 394 vss b 371 p154 b 325 vss b 246 vcc b 159 vcc b 64 n p vss b 14 vss b 113 vss b 204 vss b 287 vss b 357 vss b 384 vss b 403 vss b 414 vss b 415 vss b 408 vss b 393 vss b 370 p107 b 324 p106 b 245 p105 b 158 p193 b 63 p r p035 b 15 p036 b 114 p150 b 205 p151 b 288 vss b 358 vss b 385 vss b 404 vss b 405 vss b 406 vss b 407 vss b 392 vss b 369 p104 b 323 vss b 244 p103 b 157 p102 b 62 r t p037 b 16 p040 b 115 vss b 206 p174 b 289 vss b 359 vss b 386 vss b 387 vss b 388 vss b 389 vss b 390 vss b 391 vss b 368 p101 b 322 vss b 243 p100 b 156 avcc0 b 61 t u p041 b 17 p042 b 116 vss b 207 p175 b 290 vss b 360 vss b 361 vss b 362 vss b 363 vss b 364 vss b 365 vss b 366 vss b 367 p221 b 321 p275 b 242 p276 b 155 avrh0 b 60 u v p043 b 18 p044 b 117 p204 b 208 p205 b 291 p096 b 320 vss b 241 p222 b 154 avrl0 b 59 v w p045 b 19 p046 b 118 vss b 209 p206 b 292 p093 b 319 vss b 240 p220 b 153 avss0 b 58 w y p047 b 20 p050 b 119 vss b 210 p207 b 293 p092 b 318 p273 b 239 p095 b 152 p097 b 57 y aa p051 b 21 p052 b 120 p176 b 211 p177 b 294 p270 b 317 vss b 238 p272 b 151 p094 b 56 aa ab p053 b 22 p054 b 121 p250 b 212 p251 b 295 p267 b 316 p090 b 237 p091 b 150 p192 b 55 ab ac p252 b 23 p253 b 122 vss b 213 vss b 296 p180 b 297 p181 b 298 p182 b 299 p211 b 300 vss b 301 p061 b 302 p063 b 303 p065 b 304 p066 b 305 p072 b 306 p263 b 307 p074 b 308 p265 b 309 p080 b 310 p082 b 311 tck b 312 p083 b 313 p086 b 314 vss b 315 p266 b 236 p191 b 149 p271 b 54 ac ad vcce b 24 vcce b 123 vss b 214 vss b 215 p255 b 216 p256 b 217 vss b 218 p213 b 219 vss b 220 vss b 221 p062 b 222 vss b 223 vss b 224 p071 b 225 vss b 226 vss b 227 p076 b 228 vss b 229 vss b 230 tdi b 231 vss b 232 vss b 233 p085 b 234 vss b 235 p087 b 148 p190 b 53 ad ae vss b 25 vss b 124 p056 b 125 p254 b 126 p057 b 127 p210 b 128 p212 b 129 p060 b 130 vss b 131 vcc b 132 vcc b 133 p064 b 134 p185 b 135 p070 b 136 p262 b 137 p187 b 138 p216 b 139 p075 b 140 p264 b 141 p153 b 142 tdo b 143 trst b 144 tms b 145 vcc b 146 vss b 147 vss b 52 ae af vss b 26 vss b 27 p055 b 28 avcc1 b 29 avrh1 b 30 avrl1 b 31 avss1 b 32 vss b 33 vss b 34 vcc b 35 vcc b 36 p183 b 37 p184 b 38 p067 b 39 p073 b 40 p186 b 41 p215 b 42 p214 b 43 p217 b 44 p077 b 45 p152 b 46 p081 b 47 p084 b 48 vcc b 49 vss b 50 vss b 51 af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 top view bga-416 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 19 confidential ? pin description pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 - - - d3 p240 - a general - purpose i/o port - - - e4 p241 - a general - purpose i/o port 2 2 2 c1 p015 - r general - purpose i/o port d29 - external bu s data bit29 i/o pin trg0_0 - ppg trigger 0 input pin(0) 3 3 3 d1 p016 - r general - purpose i/o port d30 - external bus data bit30 i/o pin trg1_0 - ppg trigger 1 input pin(0) - 4 4 e3 p170 - a general - purpose i/o port ppg36_1 - ppg ch.36 output pin(1) 4 5 5 d2 p017 - r general - purpose i/o port d31 - external bus data bit31 i/o pin trg2_0 - ppg trigger 2 input pin(0) - 6 6 f4 p171 - a general - purpose i/o port ppg37_1 - ppg ch.37 output pin(1) - - - g4 p242 - a ge neral - purpose i/o port trg16_0 - ppg trigger 16 input pin(0) - - - h4 p243 - a general - purpose i/o port trg17_0 - ppg trigger 17 input pin(0) 5 7 7 e1 p020 - f general - purpose i/o port asx - external bus address strobe output pin s in3_1 - multi - function serial ch.3 serial data input pin(1) trg3_0 - ppg trigger 3 input pin(0) tin0_2 - reload timer ch.0 event input pin(2) rto5_1 - waveform generator ch.5 output pin(1) 6 8 8 e2 p021 - a general - purpose i/o port cs0x - external bus chip select 0 output pin sot3_1 - multi - function serial ch.3 serial data output pin(1) trg6_1 - ppg trigger 6 input pin(1) trg4_0 - ppg trigger 4 input pin(0) 7 9 9 f1 p022 - f general - purpose i/o port cs1x - external bus chip select 1 output pin sck3_1 - multi - function serial ch.3 clock i/o pin(1) trg7_1 - ppg trigger 7 input pin(1) trg5_0 - ppg trigger 5 input pin(0) 8 10 10 f2 p023 - a general - purpose i/o port rdx - external bus read strobe output pin scs3_1 - serial chip select 3 i/o pin(1) ppg32_0 - ppg ch.32 output pin(0) tin0_0 - reload timer ch.0 event input pin(0) - - - j3 p244 - a general - purpose i/o port ppg64_0 - ppg ch.64 output pin(0) d a t a s h e e t 20 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 - - - j4 p245 - a general - purpose i/o port ppg65_0 - ppg ch.65 output pin(0) 9 11 11 g1 p024 - f general - purpose i/o port wr0x - external bus write strobe 0 output pin sin4_1 - multi - function serial ch.4 serial data input pin(1) ppg24_0 - ppg c h.24 output pin(0) tin1_0 - reload timer ch.1 event input pin(0) rto4_1 - waveform generator ch.4 output pin(1) int15_0 - int15 external interrupt input pin(0) 10 12 12 g2 p025 - a general - purpose i/o port wr1x - external bus write strobe 1 output pin sot4_1 - multi - function serial ch.4 serial data output pin(1) ppg25_0 - ppg ch.25 output pin(0) tin2_0 - reload timer ch.2 event input pin(0) - 13 13 k3 p172 - a general - purpose i/o port ppg38_1 - ppg ch.38 out put pin(1) 11 14 14 h1 p026 - f general - purpose i/o port a00 - external bus address bit0 output pin sck4_1 - multi - function serial ch.4 clock i/o pin(1) ppg26_0 - ppg ch.26 output pin(0) tin3_0 - reload timer ch.3 event input pin(0 ) 12 15 15 j1 p027 - a general - purpose i/o port a01 - external bus address bit1 output pin scs40_1 - serial chip select 40 i/o pin(1) ppg27_0 - ppg ch.27 output pin(0) tot0_0 - reload timer ch.0 output pin(0) rto3_1 - wavefor m generator ch.3 output pin(1) - 16 16 k4 p173 - a general - purpose i/o port ppg39_1 - ppg ch.39 output pin(1) 13 17 17 j2 p030 - a general - purpose i/o port a02 - external bus address bit2 output pin scs41_1 - serial chip select 41 outpu t pin(1) ppg28_0 - ppg ch.28 output pin(0) tot1_0 - reload timer ch.1 output pin(0) 14 18 18 k1 p031 - a general - purpose i/o port a03 - external bus address bit3 output pin scs42_1 - serial chip select 42 output pin(1) ppg29_0 - ppg ch.29 output pin(0) tot2_0 - reload timer ch.2 output pin(0) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 21 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 15 19 19 k2 p032 - a general - purpose i/o port a04 - external bus address bit4 output pin scs43_1 - serial chip select 43 output pin(1) ppg30_0 - ppg ch.30 output pin(0) tot3_0 - reload timer ch.3 output pin(0) rto2_1 - waveform generator ch.2 output pin(1) - - 20 l3 p200 - q general - purpose i/o port sck12_0/scl12 - multi - function serial ch.12 clock i/o pin(0)/ i 2 c bus serial clock i/o pin an 63 - adc analog 63 input pin trg12_0 - ppg trigger 12 input pin(0) - - 21 l4 p201 - q general - purpose i/o port sot12_0/sda12 - multi - function serial ch.12 serial data output pin(0)/i 2 c bus serial data i/o pin an62 - adc analog 62 input pin trg13_0 - ppg trigger 13 input pin(0) - - 22 m3 p202 - g general - purpose i/o port sin12_0 - multi - function serial ch.12 serial data input pin(0) an61 - adc analog 61 input pin int16_0 - int16 external interrupt input pin(0) - - 23 m4 p203 - b general - purpose i/o port scs12_0 - serial chip select 12 i/o pin(0) an60 - adc analog 60 input pin 16 20 24 l1 p033 - a general - purpose i/o port a05 - external bus address bit5 output pin ppg31_0 - ppg ch.31 output pin(0) icu3_3 - input capture ch.3 input pin(3) tin4_0 - reload timer ch.4 event input pin(0) rto1_1 - waveform generator ch.1 output pin(1) sck3_2 - multi - function serial ch.3 clock i/o pin(2) 17 21 25 l2 p034 - a general - purpose i/o port a06 - external bus address bit6 output pin ocu11_1 - output compare ch.11 output pin(1) icu2_3 - input capture ch.2 input pin(3) tin5_0 - reload timer ch.5 event input pin(0) rto0_1 - waveform generator ch.0 output p in(1) sot3_2 - multi - function serial ch.3 serial data output pin(2) d a t a s h e e t 22 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 18 22 26 r3 p150 - f general - purpose i/o port rdy_1 - external bus rdy input pin (1) sot8_0/sda8 - multi - function serial ch.8 serial data output pin(0)/i 2 c bus serial da ta i/o pin ocu10_1 - output compare ch.10 output pin(1) trg6_0 - ppg trigger 6 input pin(0) icu1_3 - input capture ch.1 input pin(3) tin6_0 - reload timer ch.6 event input pin(0) 19 23 27 r4 p151 - f general - purpose i/o port s ck8_0/scl8 - multi - function serial ch.8 clock i/o pin(0)/ i 2 c bus serial clock i/o pin ocu9_1 - output compare ch.9 output pin(1) trg7_0 - ppg trigger 7 input pin(0) icu0_3 - input capture ch.0 input pin(3) tin7_0 - reload timer ch .7 event input pin(0) zin0_2 - u/d counter ch.0 zin input pin(2) dtti_1 - waveform generator ch.0 - ch.5 input pin(1) 20 24 28 r1 p035 - i general - purpose i/o port a07 - external bus address bit7 output pin sin8_0 - multi - function se rial ch.8 serial data input pin(0) ocu8_1 - output compare ch.8 output pin(1) tot4_0 - reload timer ch.4 output pin(0) ain0_0 - u/d counter ch.0 ain input pin(0) int11_0 - int11 external interrupt input pin(0) 21 25 29 r2 p036 - a general - purpose i/o port a08 - external bus address bit8 output pin scs8_0 - serial chip select 8 i/o pin(0) ocu7_1 - output compare ch.7 output pin(1) tot5_0 - reload timer ch.5 output pin(0) bin0_0 - u/d counter ch.0 bin inp ut pin(0) 22 26 30 t1 p037 - a general - purpose i/o port a09 - external bus address bit9 output pin ocu6_1 - output compare ch.6 output pin(1) tot6_0 - reload timer ch.6 output pin(0) zin0_0 - u/d counter ch.0 zin input pin(0) - 27 31 t4 p174 - a general - purpose i/o port trg8_1 - ppg trigger 8 input pin(1) - 28 32 u4 p175 - a general - purpose i/o port trg9_1 - ppg trigger 9 input pin(1) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 23 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 23 29 33 t2 p040 - a general - purpose i/o port a10 - external bus address bit10 output pin ppg23_1 - ppg ch.23 output pin(1) tot7_0 - reload timer ch.7 output pin(0) ain1_0 - u/d counter ch.1 ain input pin(0) sin0_1 - multi - function serial ch.0 serial data input pin(1) 24 30 34 u1 p041 - i general - purpose i/o port a11 - external bus address bit11 output pin sin9_0 - multi - function serial ch.9 serial data input pin(0) icu9_1 - input capture ch.9 input pin(1) bin1_0 - u/d counter ch.1 bin input pin(0) int12_0 - int12 external interr upt input pin(0) 25 31 35 u2 p042 - b general - purpose i/o port a12 - external bus address bit12 output pin sot9_0 - multi - function serial ch.9 serial data output pin(0) an47 - adc analog 47 input pin icu8_1 - input capture ch.8 inp ut pin(1) trg0_1 - ppg trigger 0 input pin(1) zin1_0 - u/d counter ch.1 zin input pin(0) 26 32 36 v1 p043 - a general - purpose i/o port a13 - external bus address bit13 output pin icu7_1 - input capture ch.7 input pin(1) trg1_1 - ppg trigger 1 input pin(1) 27 33 37 v2 p044 - a general - purpose i/o port a14 - external bus address bit14 output pin scs9_0 - serial chip select 9 i/o pin(0) icu6_1 - input capture ch.6 input pin(1) trg2_1 - ppg trigger 2 input pin(1) 28 34 38 w1 p045 - g general - purpose i/o port a15 - external bus address bit15 output pin sck9_0 - multi - function serial ch.9 clock i/o pin(0) an46 - adc analog 46 input pin icu5_1 - input capture ch.5 input pin(1) trg 3_1 - ppg trigger 3 input pin(1) tot1_2 - reload timer ch.1 output pin(2) - - 39 v3 p204 - q general - purpose i/o port sck13_0/scl13 - multi - function serial ch.13 clock i/o pin(0)/ i 2 c bus serial clock i/o pin an59 - adc analog 59 input pin ppg48_0 - ppg ch.48 output pin(0) d a t a s h e e t 24 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 - - 40 v4 p205 - q general - purpose i/o port sot13_0/sda13 - multi - function serial ch.13 serial data output pin(0)/i 2 c bus serial data i/o pin an58 - adc analog 58 input pin ppg49_0 - ppg ch.49 output pin(0) ain2_0 - u/d counter ch.2 ain input pin(0) - - 41 w4 p206 - g general - purpose i/o port sin13_0 - multi - function serial ch.13 serial data input pin(0) an57 - adc analog 57 input pin bin2_0 - u/d counter ch.2 bin input pin(0) int17_0 - int17 external interrupt input pin(0) - - 42 y4 p207 - b general - purpose i/o port scs13_0 - serial chip select 13 i/o pin(0) an56 - adc analog 56 input pin zin2_0 - u/d counter ch.2 zin input pin(0) 29 35 43 w2 p0 46 - a general - purpose i/o port a16 - external bus address bit16 output pin icu4_1 - input capture ch.4 input pin(1) trg4_1 - ppg trigger 4 input pin(1) - 36 44 aa3 p176 - a general - purpose i/o port trg10_0 - ppg trigger 10 input p in(0) 30 37 45 y1 p047 - b general - purpose i/o port a17 - external bus address bit17 output pin an45 - adc analog 45 input pin trg8_0 - ppg trigger 8 input pin(0) tin3_2 - reload timer ch.3 event input pin(2) sot0_1 - multi - f unction serial ch.0 serial data output pin(1) - 38 46 aa4 p177 - a general - purpose i/o port trg11_0 - ppg trigger 11 input pin(0) 31 39 47 y2 p050 - a general - purpose i/o port a18 - external bus address bit18 output pin trg5_1 - ppg tri gger 5 input pin(1) ppg33_0 - ppg ch.33 output pin(0) 32 40 48 aa1 p051 - a general - purpose i/o port a19 - external bus address bit19 output pin trg9_0 - ppg trigger 9 input pin(0) tx5(128)_0 - can transmission data 5 output pin(0) - - - ab3 p250 - a general - purpose i/o port ppg66_0 - ppg ch.66 output pin(0) - - - ab4 p251 - a general - purpose i/o port ppg67_0 - ppg ch.67 output pin(0) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 25 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 33 41 49 aa2 p052 - r general - purpose i/o port a20 external bus address bit20 output pin ppg34_0 - ppg ch.34 output pin(0) int14_0 - int14 external interrupt input pin(0) rx5(128)_0 - can reception data 5 input pin(0) 34 42 50 ab1 p053 - b general - purpose i/o port a21 - external bus address bit21 output pin an44 - adc analog 44 input pin ppg35_0 - ppg ch.35 output pin(0) int14_1 - int14 external interrupt input pin(1) sck0_1 - multi - function serial ch.0 clock i/o pin(1) 35 43 51 ab2 p054 - a general - purpose i/o port sysclk - ex ternal bus system clock output pin ppg36_0 - ppg ch.36 output pin(0) - - - ac1 p252 - a general - purpose i/o port - - - ac2 p253 - a general - purpose i/o port - - - ae4 p254 - a general - purpose i/o port ppg68_0 - ppg ch.68 output pin(0) - - - ad5 p255 - a general - purpose i/o port ppg69_0 - ppg ch.69 output pin(0) 38 46 54 af3 p055 - g general - purpose i/o port cs2x - external bus chip select 2 output pin sin10_0 - multi - function serial ch.10 serial data input pin(0) an 43 - adc analog 43 input pin ppg37_0 - ppg ch.37 output pin(0) tin4_1 - reload timer ch.4 event input pin(1) - 47 55 ac5 p180 - a general - purpose i/o port ppg40_0 - ppg ch.40 output pin(0) - 48 56 ac6 p181 - a general - purpose i/o port ppg41_0 - ppg ch.41 output pin(0) 39 49 57 ae3 p056 - a general - purpose i/o port cs3x - external bus chip select 3 output pin icu9_0 - input capture ch.9 input pin(0) ppg0_1 - ppg ch.0 output pin(1) icu0_1 - input capture ch. 0 input pin(1) tin5_1 - reload timer ch.5 event input pin(1) dtti_2 - waveform generator ch.0 to ch.5 input pin(2) - - - ad6 p256 - a general - purpose i/o port ppg66_1 - ppg ch.66 output pin(1) d a t a s h e e t 26 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 41 51 59 ae5 p057 - g general - purpose i/o p ort rdy _0 - external bus rdy input pin (0) sck10_1 - multi - function serial ch.10 clock i/o pin(1) an42 - adc analog 42 input pin icu8_0 - input capture ch.8 input pin(0) trg0_2 - ppg trigger 0 input pin(2) ppg1_1 - ppg c h.1 output pin(1) icu1_1 - input capture ch.1 input pin(1) tin6_1 - reload timer ch.6 event input pin(1) - 56 64 ac7 p182 - a general - purpose i/o port ppg42_0 - ppg ch.42 output pin(0) - - 65 ae6 p210 - q general - purpose i/o port s ck14_0/scl14 - multi - function serial ch.14 clock i/o pin(0)/ i 2 c bus serial clock i/o pin an55 - adc analog 55 input pin ppg50_0 - ppg ch.50 output pin(0) ain2_1 - u/d counter ch.2 ain input pin(1) - - 66 ac8 p211 - q general - purpose i/ o port sot14_0/sda14 - multi - function serial ch.14 serial data output pin(0)/i 2 c bus serial data i/o pin an54 - adc analog 54 input pin ppg51_0 - ppg ch.51 output pin(0) bin2_1 - u/d counter ch.2 bin input pin(1) - - 67 ae7 p212 - g general - purpose i/o port sin14_0 - multi - function serial ch.14 serial data input pin(0) an53 - adc analog 53 input pin frck6_0 - free - run timer 6 clock input pin(0) zin2_1 - u/d counter ch.2 zin input pin(1) int18_0 - int18 external interrupt input pin(0) - - 68 ad8 p213 - b general - purpose i/o port scs14_0 - serial chip select 14 i/o pin(0) an52 - adc analog 52 input pin frck7_0 - free - run timer 7 clock input pin(0) int17_1 - int17 external interrupt input pin(1) 46 57 69 ae8 p060 - a general - purpose i/o port scs10_0 - serial chip select 10 i/o pin(0) ppg2_1 - ppg ch.2 output pin(1) icu2_1 - input capture ch.2 input pin(1) tot5_1 - reload timer ch.5 output pin(1) int1 3_0 - int13 external interrupt input pin(0) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 27 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 47 58 70 ac10 p061 - b general - purpose i/o port sot10_1 - multi - function serial ch.10 serial data output pin(1) an41 - adc analog 41 input pin icu6_0 - input capture ch.6 input pin(0) p pg3_1 - ppg ch.3 output pin(1) icu3_1 - input capture ch.3 input pin(1) tot6_1 - reload timer ch.6 output pin(1) int13_1 - int13 external interrupt input pin(1) 48 59 71 ad11 p062 - b general - purpose i/o port scs10_1 - serial chip select 10 i/o pin(1) scs40_0 - serial chip select 40 i/o pin(0) an40 - adc analog 40 input pin ppg4_1 - ppg ch.4 output pin(1) frck0_0 - free - run timer 0 clock input pin(0) tot7_1 - reload timer ch.7 output pin(1) zin1_1 - u/d counter ch.1 zin input pin(1) 49 60 72 ac11 p063 - b general - purpose i/o port scs41_0 - serial chip select 41 output pin(0) an39 - adc analog 39 input pin ppg5_1 - ppg ch.5 output pin(1) frck1_0 - free - run timer 1 clock inp ut pin(0) bin1_1 - u/d counter ch.1 bin input pin(1) - 61 73 af12 p183 - a general - purpose i/o port ppg43_0 - ppg ch.43 output pin(0) 50 62 74 ae12 p064 - b general - purpose i/o port scs42_0 - serial chip select 42 output pin(0) an3 8 - adc analog 38 input pin frck2_0 - free - run timer 2 clock input pin(0) ain1_1 - u/d counter ch.1 ain input pin(1) ppg43_1 - ppg ch.43 output pin(1) 51 63 75 ac12 p065 - a general - purpose i/o port scs43_0 - serial chip select 43 output pin(0) frck3_0 - free - run timer 3 clock input pin(0) zin0_1 - u/d counter ch.0 zin input pin(1) ppg44_1 - ppg ch.44 output pin(1) - 64 76 af13 p184 - a general - purpose i/o port ppg44_0 - ppg ch.44 output pin(0) - 65 77 ae1 3 p185 - a general - purpose i/o port ppg45_0 - ppg ch.45 output pin(0) 52 66 78 ac13 p066 - b general - purpose i/o port sot4_2 - multi - function serial ch.4 serial data output pin(2) scs3_0 - serial chip select 3 i/o pin(0) an37 - adc analog 37 input pin frck4_0 - free - run timer 4 clock input pin(0) bin0_1 - u/d counter ch.0 bin input pin(1) d a t a s h e e t 28 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 53 67 79 af14 p067 - b general - purpose i/o port an36 - adc analog 36 input pin frck5_0 - free - run timer 5 clock input pin (0) ain0_1 - u/d counter ch.0 ain input pin(1) 54 68 80 ae14 p070 - a general - purpose i/o port icu0_2 - input capture ch.0 input pin(2) 55 69 81 ad14 p071 - g general - purpose i/o port sck4_2 - multi - function serial ch.4 clock i/o pin(2) an35 - adc analog 35 input pin icu1_2 - input capture ch.1 input pin(2) monclk - clock monitor output pin 56 70 82 ac14 p072 - g general - purpose i/o port sin4_0 - multi - function serial ch.4 serial data input pin(0) an34 - ad c analog 34 input pin icu2_2 - input capture ch.2 input pin(2) int5_0 - int5 external interrupt input pin(0) 57 71 83 af15 p073 - d general - purpose i/o port sot4_0/sda4 - multi - function serial ch.4 serial data output pin(0)/i 2 c bus seria l data i/o pin an33 - adc analog 33 input pin icu3_2 - input capture ch.3 input pin(2) - - - ae15 p262 - a general - purpose i/o port ppg70_0 - ppg ch.70 output pin(0) - - - ac15 p263 - a general - purpose i/o port ppg71_0 - ppg ch.71 output pin(0) - 72 84 af16 p186 - a general - purpose i/o port ppg46_0 - ppg ch.46 output pin(0) - 73 85 ae16 p187 - a general - purpose i/o port ppg47_0 - ppg ch.47 output pin(0) 58 74 86 ac16 p074 - e general - purpose i/o port sck4_0/scl4 - multi - function serial ch.4 clock i/o pin(0) / i 2 c bus serial clock i/o pin - - 87 af18 p214 - q general - purpose i/o port sck15_0/scl15 - multi - function serial ch.15 clock i/o pin(0)/ i 2 c bus serial clock i/o pin an51 - adc analog 51 input pin ppg52_0 - ppg ch.52 output pin(0) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 29 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 - - 88 af17 p215 - q general - purpose i/o port sot15_0/sda15 - multi - function serial ch.15 serial data output pin(0)/i 2 c bus serial data i/o pin an50 - adc analog 50 input pin frck8_0 - free - run timer 8 clock input pin(0) ppg53_0 - ppg ch.53 output pin(0) - - 89 ae17 p216 - g general - purpose i/o port sin15_0 - multi - function serial ch.15 serial data input pin(0) an49 - adc analog 49 input pin frck9_0 - free - run timer 9 cl ock input pin(0) trg12_1 - ppg trigger 12 input pin(1) int19_0 - int19 external interrupt input pin(0) - - 90 af19 p217 - b general - purpose i/o port scs15_0 - serial chip select 15 i/o pin(0) an48 - adc analog 48 input pin frc k10_0 - free - run timer 10 clock input pin(0) trg13_1 - ppg trigger 13 input pin(1) 59 75 91 ae18 p075 - f general - purpose i/o port sin3_0 - multi - function serial ch.3 serial data input pin(0) int4_0 - int4 external interrupt input pin(0 ) rx5 (128)_1 - can reception data 5 input pin(1) 60 76 92 ad17 p076 - p general - purpose i/o port sot3_0/sda3 - multi - function serial ch.3 serial data output pin(0)/i 2 c bus serial data i/o pin tx5 (128)_1 - can transmission data 5 output p in(1) 61 77 93 af20 p077 - e general - purpose i/o port sck3_0/scl3 - multi - function serial ch.3 clock i/o pin(0)/ i 2 c bus serial clock i/o pin - - - ae19 p264 - a general - purpose i/o port ppg72_0 - ppg ch.72 output pin(0) - - - ac17 p265 - a general - purpose i/o port ppg73_0 - ppg ch.73 output pin(0) 62 78 94 af21 p152 - a general - purpose i/o port scs53_0 - serial chip select 53 output pin(0) 63 79 95 ae20 p153 - g general - purpose i/o port sck5_0/scl5 - multi - function serial ch.5 clock i/o pin(0)/ i 2 c bus serial clock i/o pin an32 - adc analog 32 input pin frck1_1 - free - run timer 1 clock input pin(1) int4_1 - int4 external interrupt input pin(1) d a t a s h e e t 30 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 64 80 96 ac18 p080 - a general - purpose i/o port scs52_0 - serial chip select 52 output pin(0) ppg0_0 - ppg ch.0 output pin(0) 65 81 97 af22 p081 - g general - purpose i/o port sot5_0/sda5 - multi - function serial ch.5 serial data output pin(0)/i 2 c bus serial data i/o pin an0 - adc analog 0 inpu t pin ppg1_0 - ppg ch.1 output pin(0) - - - ae21 tdo - w jtag test data output - - - ad20 tdi - v jtag test data input 66 82 98 ac19 p082 - g general - purpose i/o port sin5_0 - multi - function serial ch.5 serial data input pin(0) an1 - a dc analog 1 input pin ppg2_0 - ppg ch.2 output pin(0) - - - ae22 trst - v jtag test reset input - - - ac20 tck - v jtag test clock input - - - ae23 tms - v jtag test mode state input 67 83 99 ac21 p083 - b general - purpose i/o port scs50_0 - serial chip select 50 i/o pin(0) an2 - adc analog 2 input pin ppg3_0 - ppg ch.3 output pin(0) 68 84 100 af23 p084 - b general - purpose i/o port scs51_0 - serial chip select 51 output pin(0) an3 - adc analog 3 input pin ppg4_0 - ppg ch.4 output pin(0) 69 85 101 ad23 p085 - a general - purpose i/o port ppg5_0 - ppg ch.5 output pin(0) 70 86 102 ac22 p086 - c general - purpose i/o port dao1 - dac analog 1 output pin ppg6_0 - ppg ch.6 output pin(0) 71 87 103 ad25 p 087 - c general - purpose i/o port dao0 - dac analog 0 output pin ppg7_0 - ppg ch.7 output pin(0) int8_0 - int8 external interrupt input pin(0) - - - ac24 p266 - a general - purpose i/o port ppg74_0 - ppg ch.74 output pin(0) - - - ab2 3 p267 - a general - purpose i/o port ppg75_0 - ppg ch.75 output pin(0) - 90 106 ad26 p190 - a general - purpose i/o port tin0_1 - reload timer ch.0 event input pin(1) - 91 107 ac25 p191 - a general - purpose i/o port tin1_1 - reload timer ch .1 event input pin(1) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 31 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 74 92 108 ab24 p090 - b general - purpose i/o port an4 - adc analog 4 input pin icu0_0 - input capture ch.0 input pin(0) tin2_1 - reload timer ch.2 event input pin(1) - - - aa23 p270 - a general - purpose i/o port ppg76_0 - ppg ch.76 output pin(0) - - - ac26 p271 - a general - purpose i/o port ppg77_0 - ppg ch.77 output pin(0) 75 93 109 ab25 p091 - b general - purpose i/o port an5 - adc analog 5 input pin ppg41_1 - ppg ch.41 output pin(1) icu1 _0 - input capture ch.1 input pin(0) tin3_1 - reload timer ch.3 event input pin(1) 76 94 110 y23 p092 - b general - purpose i/o port an6 - adc analog 6 input pin ppg40_1 - ppg ch.40 output pin(1) icu2_0 - input capture ch.2 input pi n(0) tot0_1 - reload timer ch.0 output pin(1) - 95 111 ab26 p192 - a general - purpose i/o port ppg24_1 - ppg ch.24 output pin(1) tot1_1 - reload timer ch.1 output pin(1) - - - aa25 p272 - a general - purpose i/o port ppg78_0 - ppg ch .78 output pin(0) - - - y24 p273 - a general - purpose i/o port ppg79_0 - ppg ch.79 output pin(0) 77 96 112 w23 p093 - j general - purpose i/o port tx0(128)_1 - can transmission data 0 output pin(1) sin11_0 - multi - function serial ch.11 ser ial data input pin(0) an7 - adc analog 7 input pin icu4_2 - input capture ch.4 input pin(2) ppg16_1 - ppg ch.16 output pin(1) icu3_0 - input capture ch.3 input pin(0) tot2_1 - reload timer ch.2 output pin(1) 78 97 113 aa26 p0 94 - b general - purpose i/o port an8 - adc analog 8 input pin icu4_0 - input capture ch.4 input pin(0) tot3_1 - reload timer ch.3 output pin(1) 79 98 114 y25 p095 - b general - purpose i/o port tx0(128)_0 - can transmission data 0 out put pin(0) scs11_0 - serial chip select 11 i/o pin(0) an9 - adc analog 9 input pin d a t a s h e e t 32 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 80 99 115 v23 p096 - g general - purpose i/o port rx0(128)_0 - can reception data 0 input pin(0) sot11_0/sda11 - multi - function serial ch.11 serial da ta output pin(0)/i 2 c bus serial data i/o pin an10 - adc analog 10 input pin int0_0 - int0 external interrupt input pin(0) 81 100 116 y26 p097 - g general - purpose i/o port sck11_0/scl11 - multi - function serial ch.11 clock i/o pin(0)/ i 2 c bus serial clock i/o pin an11 - adc analog 11 input pin icu5_0 - input capture ch.5 input pin(0) ppg17_1 - ppg ch.17 output pin(1) - - 117 w25 p220 - p general - purpose i/o port sck16_0/scl16 - multi - function serial ch.16 clock i/o pin(0)/ i 2 c bus serial clock i/o pin icu10_0 - input capture ch.10 input pin(0) ppg48_1 - ppg ch.48 output pin(1) - - 118 u23 p221 - p general - purpose i/o port sot16_0/sda16 - multi - function serial ch.16 serial data output pin(0)/i 2 c bu s serial data i/o pin icu11_0 - input capture ch.11 input pin(0) ppg49_1 - ppg ch.49 output pin(1) - - 119 v25 p222 - i general - purpose i/o port sin16_0 - multi - function serial ch.16 serial data input pin(0) ppg54_0 - ppg ch.54 out put pin(0) int20_0 - int20 external interrupt input pin(0) - - - u24 p275 - a general - purpose i/o port ppg67_1 - ppg ch.67 output pin(1) - - - u25 p276 - a general - purpose i/o port trg16_1 - ppg trigger 16 input pin(1) ppg86_1 - p pg ch.86 output pin(1) 85 104 123 t25 p100 - g general - purpose i/o port sck7_0/scl7 - multi - function serial ch.7 clock i/o pin(0)/ i 2 c bus serial clock i/o pin an12 - adc analog 12 input pin ppg8_0 - ppg ch.8 output pin(0) 86 105 124 t2 3 p101 - g general - purpose i/o port sot7_0/sda7 - multi - function serial ch.7 serial data output pin(0)/i 2 c bus serial data i/o pin an13 - adc analog 13 input pin ppg9_0 - ppg ch.9 output pin(0) tx3(128)_0 - can transmission data 3 o utput pin(0) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 33 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 87 106 125 r26 p102 - g general - purpose i/o port sin7_0 - multi - function serial ch.7 serial data input pin(0) an14 - adc analog 14 input pin ppg10_0 - ppg ch.10 output pin(0) int10_0 - int10 external interrupt input pi n(0) rx3(128)_0 - can reception data 3 input pin(0) 88 107 126 r25 p103 - h general - purpose i/o port scs73_0 - serial chip select 73 output pin(0) an15 - adc analog 15 input pin ppg11_0 - ppg ch.11 output pin(0) 89 108 127 r23 p10 4 - h general - purpose i/o port scs72_0 - serial chip select 72 output pin(0) an16 - adc analog 16 input pin ppg12_0 - ppg ch.12 output pin(0) 90 109 128 p25 p105 - h general - purpose i/o port scs71_0 - serial chip select 71 output p in(0) an17 - adc analog 17 input pin ppg13_0 - ppg ch.13 output pin(0) 91 110 129 p24 p106 - h general - purpose i/o port scs70_0 - serial chip select 70 i/o pin(0) an18 - adc analog 18 input pin ppg14_0 - ppg ch.14 output pin( 0) 92 111 130 p23 p107 - u general - purpose i/o port an19 - adc analog 19 input pin ppg15_0 - ppg ch.15 output pin(0) txena_1 - flexray ch.a operation enable output(1) - 112 131 p26 p193 - a general - purpose i/o port ppg25_1 - ppg c h.25 output pin(1) 93 113 132 n23 p154 - u general - purpose i/o port an20 - adc analog 20 input pin txda_1 - flexray ch.a data output(1) 94 114 133 l26 p155 - s general - purpose i/o port an21 - adc analog 21 input pin rxda_1 - flexr ay ch.a data input(1) 95 115 136 l25 nmix n m non - maskable interrupt input pin - - - l24 p277 - a general - purpose i/o port trg17_1 - ppg trigger 17 input pin(1) ppg87_1 - ppg ch.87 output pin(1) 96 116 137 l23 p110 - b general - purpose i/o po rt tx1(128)_0 - can transmission data 1 output pin(0) scs63_0 - serial chip select 63 output pin(0) an22 - adc analog 22 input pin d a t a s h e e t 34 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 97 117 138 j26 p111 - g general - purpose i/o port rx1(128)_0 - can reception data 1 input pin(0) scs62_0 - serial chip select 62 output pin(0) an23 - adc analog 23 input pin int1_0 - int1 external interrupt input pin(0) 98 118 139 k26 p112 - u general - purpose i/o port an24 - adc analog 24 input pin ppg16_0 - ppg ch.16 output pin(0) rto0_0 - waveform generator ch.0 output pin(0) txenb_1 - flexray ch.b operation enable output(1) 99 119 140 k25 p113 - u general - purpose i/o port an25 - adc analog 25 input pin ppg17_0 - ppg ch.17 output pin(0) rto1_0 - waveform generator ch.1 output pin(0) txdb_1 - flexray ch.b data output(1) - 120 141 h26 p194 - a general - purpose i/o port frck5_1 - free - run timer 5 clock input pin(1) ppg26_1 - ppg ch.26 output pin(1) - 121 142 j25 p195 - a general - purpose i/o port frck4_1 - free - run timer 4 clock input pin(1) ppg27_1 - ppg ch.27 output pin(1) - - - g26 p280 - a general - purpose i/o port ppg80_0 - ppg ch.80 output pin(0) - - - h25 p281 - a general - purpose i/o port ppg81_0 - ppg ch.81 output pin(0) 100 122 143 k23 p114 - s general - purpose i/o port scs61_0 - serial chip select 61 output pin(0) an26 - adc analog 26 input pin ppg18_0 - ppg ch.18 output pin(0) rto2_0 - waveform generator ch.2 output pin(0) rxdb_1 - flexray ch.b data input(1) 101 123 144 f26 p115 - g general - purpose i/o port rx1(128)_1 - can reception data 1 input pin(1) sot6_0/sda6 - multi - function serial ch.6 serial data output pin(0)/i 2 c bus serial data i/o pin an2 7 - adc analog 27 input pin ppg19_0 - ppg ch.19 output pin(0) rto3_0 - waveform generator ch.3 output pin(0) int1_1 - int1 external interrupt input pin(1) 102 124 145 g25 p116 - g general - purpose i/o port sck6_0/scl6 - multi - funct ion serial ch.6 clock i/o pin(0)/ i 2 c bus serial clock i/o pin an28 - adc analog 28 input pin ppg20_0 - ppg ch.20 output pin(0) rto4_0 - waveform generator ch.4 output pin(0) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 35 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 103 125 146 h24 p117 - b general - purpose i/o port scs60_0 - serial chip select 60 i/o pin(0) an29 - adc analog 29 input pin ppg21_0 - ppg ch.21 output pin(0) rto5_0 - waveform generator ch.5 output pin(0) - 126 147 j23 p196 - a general - purpose i/o port frck3_1 - free - run timer 3 clock i nput pin(1) ppg28_1 - ppg ch.28 output pin(1) - - - e26 p282 - a general - purpose i/o port ppg82_0 - ppg ch.82 output pin(0) - - - f25 p283 - a general - purpose i/o port ppg83_0 - ppg ch.83 output pin(0) 104 127 148 h23 p120 - s general - purpose i/o port an30 adc analog 30 input pin ocu6_0 - output compare ch.6 output pin(0) ppg22_0 - ppg ch.22 output pin(0) int9_0 - int9 external interrupt input pin(0) rx 4 (128)_0 - can reception data 4 input pin(0) 105 128 149 d26 p121 - a general - purpose i/o port ocu7_0 - output compare ch.7 output pin(0) ppg23_0 - ppg ch.23 output pin(0) tx 4 (128)_0 - can transmission data 4 output pin(0) 106 129 150 e25 p122 - j general - purpose i/o port sin6_0 - mu lti - function serial ch.6 serial data input pin(0) an31 - adc analog 31 input pin ocu8_0 - output compare ch.8 output pin(0) int9_1 - int9 external interrupt input pin(1) - - 151 g23 p225 - p general - purpose i/o port sck17_0/scl17 - multi - function serial ch.17 clock i/o pin(0)/ i 2 c bus serial clock i/o pin ppg55_0 - ppg ch.55 output pin(0) - - 152 d25 p226 - p general - purpose i/o port sot17_0/sda17 - multi - function serial ch.17 serial data output pin(0)/i 2 c bus serial da ta i/o pin ppg56_0 - ppg ch.56 output pin(0) - - 153 e24 p227 - i general - purpose i/o port sin17_0 - multi - function serial ch.17 serial data input pin(0) ppg57_0 - ppg ch.57 output pin(0) int21_0 - int21 external interrupt input pi n(0) - 130 154 f23 p197 - a general - purpose i/o port ppg29_1 - ppg ch.29 output pin(1) d a t a s h e e t 36 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 107 131 155 e23 p123 - r general - purpose i/o port ocu9_0 - output compare ch.9 output pin(0) stopwt_1 - flexray stopwatch input(1) 110 134 158 c26 d ebugif - l debugif i/o pin for debug (ocd) - - - c25 p284 - a general - purpose i/o port ppg84_0 - ppg ch.84 output pin(0) - - - d22 p285 - a general - purpose i/o port ppg85_0 - ppg ch.85 output pin(0) - 135 159 c22 p160 - a general - purpose i/o port ppg30_1 - ppg ch.30 output pin(1) - 136 160 d21 p161 - a general - purpose i/o port ppg31_1 - ppg ch.31 output pin(1) - - - b22 p286 - a general - purpose i/o port trg18_0 - ppg trigger 18 input pin(0) - - - c21 p287 - a general - purp ose i/o port trg19_0 - ppg trigger 19 input pin(0) 111 137 161 - p124 - a general - purpose i/o port ocu10_0 - output compare ch.10 output pin(0) trst - jtag test reset input - - - d20 p124 - a general - purpose i/o port ocu10_0 - out put compare ch.10 output pin(0) 112 138 162 - p125 - a general - purpose i/o port ocu11_0 - output compare ch.11 output pin(0) tms - jtag test mode state input - - - a22 p125 - a general - purpose i/o port ocu11_0 - output compare ch.11 out put pin(0) - - 163 b21 p230 - p general - purpose i/o port sck18_0/scl18 - multi - function serial ch.18 clock i/o pin(0)/ i 2 c bus serial clock i/o pin ocu12_0 - output compare ch.12 output pin(0) ppg58_0 - ppg ch.58 output pin(0) - - 164 c 20 p231 - p general - purpose i/o port sot18_0/sda18 - multi - function serial ch.18 serial data output pin(0)/i 2 c bus serial data i/o pin ocu13_0 - output compare ch.13 output pin(0) ppg59_0 - ppg ch.59 output pin(0) - - 165 d19 p232 - i ge neral - purpose i/o port sin18_0 - multi - function serial ch.18 serial data input pin(0) ppg60_0 - ppg ch.60 output pin(0) int22_0 - int22 external interrupt input pin(0) - - 166 c19 p233 - a general - purpose i/o port scs18_0 - serial chip select 18 i/o pin(0) ppg61_0 - ppg ch.61 output pin(0) int16_1 - int16 external interrupt input pin(1) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 37 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 - - - d18 p290 - a general - purpose i/o port trg20_0 - ppg trigger 20 input pin(0) ppg64_1 - ppg ch.64 output pin(1) - - - b18 p291 - a general - purpose i/o port trg21_0 - ppg trigger 21 input pin(0) ppg65_1 - ppg ch.65 output pin(1) 113 139 167 - p126 - f general - purpose i/o port sin0_0 - multi - function serial ch.0 serial data input pin(0) int6_0 - int 6 external interrupt input pin(0) tdi - jtag test data input - - - c18 p126 - f general - purpose i/o port sin0_0 - multi - function serial ch.0 serial data input pin(0) int6_0 - int6 external interrupt input pin(0) 114 140 168 - p127 - a g eneral - purpose i/o port sot0_0 - multi - function serial ch.0 serial data output pin(0) tdo - jtag test data output - - - c17 p127 - a general - purpose i/o port sot0_0 - multi - function serial ch.0 serial data output pin(0) 115 141 169 - p1 30 - f general - purpose i/o port sck0_0 - multi - function serial ch.0 clock i/o pin(0) tck - jtag test clock input - - - d17 p130 - f general - purpose i/o port sck0_0 - multi - function serial ch.0 clock i/o pin(0) - 142 170 c16 p162 - a gen eral - purpose i/o port trg5_2 - ppg trigger 5 input pin(2) - 143 171 d16 p163 - a general - purpose i/o port trg6_2 - ppg trigger 6 input pin(2) 116 144 172 b23 md0 - k mode pin 0 117 145 173 a23 md1 - k mode pin 1 118 146 174 a20 x0 - n main clock oscillation input pin 119 147 175 a19 x1 - n main clock oscillation output pin 121 149 177 a17 p135 - a general - purpose i/o port dtti_0 - waveform generator ch.0 to ch.5 input pin(0) x1a - o sub clock oscillation output pin 122 150 178 a16 p136 - a general - purpose i/o port x0a - o sub clock oscillation input pin 123 151 179 b15 rstx n m external reset input pin 126 154 182 d15 p133 - a general - purpose i/o port tx2(128)_0 - can transmission data 2 output pin(0) d a t a s h e e t 38 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 127 155 183 d 14 p134 - f general - purpose i/o port rx2(128)_0 - can reception data 2 input pin(0) scs1_1 - serial chip select 1 i/o pin(1) icu7_0 - input capture ch.7 input pin(0) int7_0 - int7 external interrupt input pin(0) 131 159 187 a10 p00 0 - f general - purpose i/o port d16 - external bus data bit16 i/o pin sin1_0 - multi - function serial ch.1 serial data input pin(0) tioa0_1 - base timer ch.0 tioa output pin(1) int2_0 - int2 external interrupt input pin(0) 132 160 18 8 b10 p001 - r general - purpose i/o port d17 - external bus data bit17 i/o pin sot1_0 - multi - function serial ch.1 serial data output pin(0) tioa1_1 - base timer ch.1 tioa i/o pin(1) 133 161 189 a9 p002 - f general - purpose i/o port d 18 - external bus data bit18 i/o pin sck1_0 - multi - function serial ch.1 clock i/o pin(0) tiob0_1 - base timer ch.0 tiob input pin(1) 134 162 190 b9 p003 - t general - purpose i/o port d19 - external bus data bit19 i/o pin sin2_0 - multi - function serial ch.2 serial data input pin(0) tiob1_1 - base timer ch.1 tiob input pin(1) int3_0 - int3 external interrupt input pin(0) txena_0 - flexray ch.a operation enable output(0) 135 163 191 a8 p004 - r general - purpose i/o p ort d20 - external bus data bit20 i/o pin sot2_0 - multi - function serial ch.2 serial data output pin(0) txda_0 - flexray ch.a data output(0) - 164 192 d12 p164 - a general - purpose i/o port ppg32_1 - ppg ch.32 output pin(1) 136 165 193 b8 p005 - f general - purpose i/o port d21 - external bus data bit21 i/o pin sck2_0 - multi - function serial ch.2 clock i/o pin(0) adtg0_1 - a/d converter external trigger input pin 0(1) int7_1 - int7 external interrupt input pin( 1) rxda_0 - flexray ch.a data input(0) - 166 194 c11 p165 - a general - purpose i/o port ppg33_1 - ppg ch.33 output pin(1) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 39 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 137 167 195 a7 p006 - r general - purpose i/o port d22 - external bus data bit22 i/o pin scs2_0 - serial chip s elect 2 i/o pin(0) adtg1_1 - a/d converter external trigger input pin 1(1) int2_1 - int2 external interrupt input pin(1) txenb_0 - flexray ch.b operation enable output(0) 138 168 196 b7 p007 - r general - purpose i/o port d23 - exter nal bus data bit23 i/o pin txdb_0 - flexray ch.b data output(0) - - - d11 p292 - a general - purpose i/o port - - - c10 p293 - a general - purpose i/o port - 169 197 d10 p166 - a general - purpose i/o port ppg34_1 - ppg ch.34 output pin(1) 139 17 0 198 a6 p010 - r general - purpose i/o port d24 - external bus data bit24 i/o pin rxdb_0 - flexray ch.b data input(0) - - 199 c9 p234 - p general - purpose i/o port sck19_0/scl19 - multi - function serial ch.19 clock i/o pin(0)/ i 2 c bus seria l clock i/o pin ppg62_0 - ppg ch.62 output pin(0) - - 200 d9 p235 - p general - purpose i/o port sot19_0/sda19 - multi - function serial ch.19 serial data output pin(0)/i 2 c bus serial data i/o pin ppg63_0 - ppg ch.63 output pin(0) ain3_ 0 - u/d counter ch.3 ain input pin(0) - - 201 d8 p236 - i general - purpose i/o port sin19_0 - multi - function serial ch.19 serial data input pin(0) trg14_0 - ppg trigger 14 input pin(0) bin3_0 - u/d counter ch.3 bin input pin(0) int2 3_0 - int23 external interrupt input pin(0) - - 202 d7 p237 - a general - purpose i/o port scs19_0 - serial chip select 19 i/o pin(0) trg15_0 - ppg trigger 15 input pin(0) z in3_0 - u/d counter ch.3 zin input pin(0) 140 171 203 b6 p011 - r general - purpose i/o port wot - rtc output pin d25 - external bus data bit25 i/o pin sot2_1 - multi - function serial ch.2 serial data output pin(1) tioa0_0 - base timer ch.0 tioa output pin(0) int3_1 - int3 external interrupt input pin(1) 141 172 204 a5 p012 - r general - purpose i/o port d26 - external bus data bit26 i/o pin tiob0_0 - base timer ch.0 tiob input pin(0) stopwt_0 - flexray stopwatch input(0) d a t a s h e e t 40 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 - - - c6 p294 - a general - purpose i/o port ppg86_ 0 - ppg ch.86 output pin(0) - - - c5 p295 - a general - purpose i/o port ppg87_0 - ppg ch.87 output pin(0) - 173 205 d6 p167 - a general - purpose i/o port ppg35_1 - ppg ch.35 output pin(1) - - - c4 p296 - a general - purpose i/o port - - - d5 p 297 - a general - purpose i/o port 142 174 206 b5 p013 - r general - purpose i/o port d27 - external bus data bit27 i/o pin tioa1_0 - base timer ch.1 tioa i/o pin(0) 143 175 207 a4 p014 - r general - purpose i/o port d28 - external bus data b it28 i/o pin tiob1_0 - base timer ch.1 tiob input pin(0) 40 50 58 af4 avcc1 - - a/d, d/a converter unit1 analog power supply pin 84 103 122 t26 avcc0 - - a/d, d/a converter unit0 analog power supply pin 42 52 60 af5 avrh1 - - a/d converter unit1 u pper limit reference voltage pin 83 102 121 u26 avrh0 - - a/d converter unit0 upper limit reference voltage pin 43 53 61 - avss1/avrl1 - - a/d, d/a converter unit1 gnd/ a/d converter unit1 lower limit reference voltage pin - - - af7 avss1 - - a/d, d/a c onverter unit1 gnd - - - af6 avrl1 - - a/d converter unit1 lower limit reference voltage pin 82 101 120 - avss0/avrl0 - - a/d, d/a converter unit0 gnd/ a/d converter unit0 lower limit reference voltage pin - - - w26 avss0 - - a/d, d/a converter unit0 gn d - - - v26 avrl0 - - a/d converter unit0 lower limit reference voltage pin 130 158 186 a13 c - - external capacity connection output pin - - 63 af10 vcc - - power supply (1) 45 55 104 af11 72 88 134 a e 10 109 133 157 a e 11 124 152 180 a e 2 4 - - - af24 - - - n25 - - - n26 - - - a24 - - - b24 - - - a14 - b14 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 41 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 36 44 52 m 1 vcce - - power supply (2) 128 156 184 m2 144 176 208 a d2 - - - ad 1 - - - a1 1 - - - b11 - - - b3 - - - a3 1 1 1 a1 vss - - gnd 37 45 53 b2 44 54 62 p 1 73 89 105 p 2 108 132 135 af1 120 148 156 ae2 125 153 176 af8 129 157 181 af9 - - 185 ae9 - - - ad10 - - - af26 - - - ae25 - - - m26 - - - m25 - - - a26 - - - b25 - - - a2 1 - - - a 18 - - - b1 6 - - - a1 5 - - - a1 2 - - - b1 2 - - - a2,a25 - - - b1, b4 - - - b1 3,b17 - - - b19,b20 - - - b26 - - - c 2 ,c 3 - - - c7,c8 - - - c1 2 ,c1 3 - - - c1 4 ,c1 5 - - - c23,c24 - - - d 4 ,d 13 - - - d 23 ,d2 4 - - - f3,f24 - - - g3,g24 - - - h2,h3 - - - j24 - - - k10 - k17 d a t a s h e e t 42 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential pin number pin name polarity i/o circuit type * 1 function * 2 144 176 208 bga 416 - - - k24 vss - - gnd - - - l10 - l17 - - - m10 - m17 - - - m23,m24 - - - n1 - n4 - - - n10 - n17 - - - n24 - - - p3,p4 - - - p10 - p17 - - - r10 - r17 - - - r24 - - - t3 - - - t10 - t17 - - - t24 - - - u3 - - - u10 - u17 - - - v24 - - - w3 , w24 - - - y3 - - - aa24 - - - ac3,ac4 - - - ac 9 ,ac23 - - - - - - ad3 ,ad4 ad7,ad9 - - - ad12,ad13 - - - ad15,ad16 - - - ad18,ad19 - - - ad21,ad22 - - - ad24 - - - ae1,ae26 - - - af2,af25 *1: for the i/o circuit types, see " ? i/ o circuit type " . *2: for switching, see " i/o port" in hardware manual. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 43 confidential ? i/o circuit type type circuit remarks a - general - purpose i/o port - output 4ma - pull - up resistor control 50k - automotive input b - analog input, general - purpose i/o port - output 4ma - pull - up resistor control 50k - automotive input c - dac output, general - purpose i/o port - output 4ma - pull - up resistor control 50k - automotive input d - i 2 c analog input , general - purpose i/o port - output 3ma - pull - up resistor control 50k - i 2 c hysteresis input pull - up control digital output digital output i 2 c input standby control analog input pull - up control digital output digital output automotive input standby control dac output analog input pull - up control digital output digital output automotive input standby control pull - up control digital output standby control automotive input digital output d a t a s h e e t 44 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential type circuit remarks e - i 2 c,general - purpose i/o port - output 3ma - pull - up resistor control 50k - i 2 c hysteresis input f - general - purpose i/o p ort - output 4ma - pull - up resistor control 50k - cmos hysteresis input g - analog input , general - purpose i/o port - output 4ma - pull - up resistor control 50k - cmos hysteresis input h - analog input , general - purpose i/o port - output 12ma - pull - up resistor control 50k - automotive input pull - up control digital output digital output automotive input standby control analog input pull - up control digital output digital output cmos - hys input standby control analog input pull - up control digital output digital output c mos - hys input standby control pull - up control digital output digital output i 2 c input standby control d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 45 confidential type circuit remarks i - general - purpose i/o port (5v tolerant) - output 4ma - cmos hysteresis input j - analog input , g eneral - purpose i/o port (5v tolerant) - output 4ma - cmos hysteresis input k - mode i/o - cmos hysteresis input l - open - drain i/o - output 25ma (nch open drain) - ttl input m - h ysteresis input - pull - up resistor 50k ttl input digital output mode input control digital output digital output cmos - hys input standby control analog input digital output digital output cmos - hys input standby control cmos - hys input d a t a s h e e t 46 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential type circuit remarks n - main oscillation i/o o - sub oscillation i/o p - general - purpose i/o port - output 4ma - output 3ma (nch open drain) - pull - up resistor control 50k - cmos hysteresis input q - analog input , general - purpose i/o port - output 4ma - output 3ma (nch open drain) - pull - up resistor control 50k - cmos hysteresis input r - general - purpose i/o port - output 4ma - output 4ma ( flexray output) - pull - up resistor control 50k - automotive input - cmos hysteresis input pull - up control digital output digital output cmos - hys input standby control standby control automotive input pull - up control digital output digital output cmos - hys input standby control analog input pu ll - up control digital output digital output cmos - hys input standby control input standby control input standby control d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 47 confidential type circuit remarks s - analog input, general - purpose i/o port - output 4ma - output 4ma ( flexray output) - pull - up resistor control 50k - automotive input - cmos hysteresis input t - general - purpose i/o port - output 4ma - output 4ma ( flexray output) - pull - up resistor control 50k - cmos hysteresis input u - analog input, general - purpose i/o port - output 4ma - output 4ma ( flexray output) - pull - up resistor control 50k - automotive input v - cmos hysteresis input w - o utput 4ma digital output digital output cmos - hys input standby control pull - up control digital output digital output standby control automotive input analog input pull - up control digital output digital output standby co ntrol cmos - hys input pull - up control digital output digital output standby control automotive input standby control cmos - hys input analog input d a t a s h e e t 48 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes prec autions that must be observed to minimize the chance of failure and to obtain higher reliability from your spansion semiconductor devices. 1. precautions for product design this section describes precautions when designing electronic equipment using semicondu ctor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? re commended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within t he recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. user s considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power s upply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to perma nent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large curren t flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of op eration. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high volta ges, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of lat ch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute ma ximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power - on sequence. code: ds00 - 00004 - 2 e a d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 49 confidential ? observance of safety regulations and standards most countries in th e world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor de vices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. ? precautions related to usage of devices spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 2. precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during s oldering, you should only mount under spansion 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be don e by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liq uid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to spansion recommended mounting conditions. if socket mount ing is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased su sceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with spansion ranking of recommended conditions. d a t a s h e e t 50 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be red uced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. s tore products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, spansion packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the spansion recommended conditions for baking. condition: 125 c /24 h ? static elect ricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generatio n may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on t he level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other hi ghly static - prone materials for storage of completed board assemblies. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 51 confidential 3. precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to ch emical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments invol ving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of spansion products in other special environmental conditions should consult with sales representatives. please check the latest handling precautions at the following url. http://www.spansion.com/fjdocuments/fj/datasheet/e - ds/ds00 - 00004.pdf d a t a s h e e t 52 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? handling devices this section explains the latch - up prevention and pin processing. ? for latch - up prevention if a voltage higher than v cc ( v cce in case of terminal corresponding to v cce power supply. ) or a voltage lower than v ss is applied to an i/o pin, o r if a voltage exceeding the ratings is applied between v cc and v ss pins or v cce and v ss pins , a latch - up may occur in cmos ic. if the latch - up occurs, the power supply current increases excessively and device elements may be damaged by heat. take care to prevent any voltage from exceeding the maximum ratings in device application. also, the analog power supply (a v cc , avrh) , analog input and digital power supply ( v cce ) must not be exceed the digital power supply ( v cc ) when the power supply to the analog sys tem and digital power supply ( v cce ) are turned on or off. in the correct power - on sequence of the microcontroller, turn on the digital power supply ( v cc ) , analog power supplies (a v cc , avrh) and digital power supply ( v cce ) simultaneously. or, turn on the di gital power supply ( v cc ), and then turn on analog power supplies (a v cc , avrh) and digital power supply ( v cce ) . ? treatment of unused pins if unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch - up. conn ect at least a 2k resistor to each of the unused pins for pull - up or p u ll - down processing. also, if i/o pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated in the same way as for the inp ut pins. ? power supply pins the device is designed to ensure that if the device contains multiple v cc or v ss pins, the pins that should be at the same potential are interconnected to prevent latch - up or other malfunctions. further, connect these pins to an external power s upply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. as shown in f igure 1 , all vss power supply pins must be treated in th e similar way. if multiple vcc or vss systems are connected, the device cannot operate correctly even within the guaranteed operating range. figure 1 power supply input pins the power supply pins shou ld be connected to v cc and v ss pins of this device at the low impedance from the power supply source. in the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of c pin is recommended to use as a bypass capacito r between v cc and v ss pins . vss vss vcc vcc vss vcc vcc vss vss vcc d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 53 confidential ? crystal oscillation circuit an external noise to the x0 or x1 pin may cause a device malfunction. the printed circuit board must be designed to lay out x0 and x1 pins, crystal oscillator (or ceramic resonator), and the bypass c apacitor to be grounded to the close position to the device. the printed circuit board artwork is recommended to surround the x0 and x1 pins by ground circuits. ? mode pins ( md1, md0 ) connec t the md1 and md0 m ode pin s to the v cc or v ss pin directly. to preven t an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode pin and v cc or v ss pin on the printed circuit board. also, use the low - impedance pin connection. ? during power - on to prevent a malfunction of the voltage step - down circuit built in the device, set the voltage rising time to have 50 s or longer (between 0.2v and 2.7v) during power - on. ? notes during pll clock operation when the pll clock is selected and if the oscillator is disconnected or if the input is sto pped, this clock may continue to operate at the free running frequency of the self - oscillator circuit built in the pll clock. this operation is not guaranteed. ? treatment of a/d converter power supply pins connect the pins to have a v cc =avrh=v cc and av ss /avr l=v ss even if the a/d converter is not used. ? no tes on using external clock an external clock is not supported. none of the external d irect clock input can be used for both main clock and sub clock . ? power - on sequence of a/d converter analog inputs be sure t o turn on the digital power supply ( v cc , v cce ) first, and then turn on the a/d converter power supplies (avcc, avrh, avrl) and analog inputs (an0 to an 63 ). also, turn off the a/d converter power supplies and analog inputs first, and then turn off the digit al power supply ( v cc , v cce ). when the avrh pin voltage is turned on or off, it must not exceed a v cc . even if a common analog input pin is used as an input port, its input voltage must not exceed av cc . (however, the analog power supply and digital power sup ply can be turned on or off simultaneously.) ? treatment of c pin this device contains a voltage step - down circuit. a capacitor must always be connected to the c pin to assure the internal stabilization of the device. for the standard values, see the "recomm ended operating conditions" of the latest data sheet. note: please see the latest data sheet for a detailed specification of the operation voltage. ? function switching of a multiplexed port t o switch between the port function and the multiplexed pin functi on, use the pfr (port function register). however, if a pin is also used for an external bus, its function is switched by the external bus setting. for details, see " i/o ports" in the hardware manual . d a t a s h e e t 54 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? low - power consumption mode t o transit t o the sleep mo de, watch mode, stop mode, watch mode(power - off) or stop mode(power - off), follow the procedure explained in "activating the sleep mode, watch mode, or stop mode" or "activating the watch mode (power - off) or stop mode (power - off) " of " power c onsumption cont rol" in the hardware manual . take the following notes when using a monitor debugger. do not set a break point for the low - power consumption transition program. do not execute an operation step for the low - power consumption transition program. ? notes when wr iting data in a register having the status flag when writing data in the register that has a status flag (especially, an interrupt request flag) to control function , tak ing care not to clear its status flag erroneously must be followed. the program must be written not to clear the flag to the status bit, and then to set the control bits to have the desired value. especially, if multiple control bits are used, the bit instruction cannot be used. (the bit instruction can access to a single bit only.) by t he byte, half - word, or word access , data is written to the control bits and status flag simultaneously. during this time, take care not to clear other bits (in this case, the bits of status flag) erroneously. note: these points can be ignore d because the bit instructions are already taken the points into consideration . d a t a s h e e t m arch 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 55 confidential ? block diagram ? mb91f52 7r , mb91f52 8r from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data on chip bus layer 2 external bus i / f peripheral bus bridge can prescaler watchdog timer (sw and hw) delay interrupt interrupt controller rtc / wdt1 calibration i/o port setting low power consumption setting register 16 32 wild register i / o port on chip bus layer 1 debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on chip bus(ahb) xbs clock control (clock setting, main timer, sub timer, pll timer) m p u 32bit peripheral bus (apb) clock control (divide control) bus performance counter 16bit peripheral bus backup ram 16kb timing protection unit ppg(44ch) reload timer (8ch) 8bit da converter (2ch) external interrupt input (16ch) 32bit output compare (6ch) base timer (2ch) u/d counter (2ch) 32bit free - run timer (3ch) 32bit input capture (6ch) multi - function serial interface (12ch) dmac (16 ch) can ( 6 ch) crc operation mode register wave generator (6ch) 12bit ad converter (32ch + 16ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low voltage detection (external power supply low voltage detection) reset control register nmi flash ? main flash 1600kb/2112kb ? work flash 64kb ram 192kb/192kb clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low voltage detection (internal power supply low voltage detection) rstx nmix md0,md1,p006 rx,tx d,a,asx,cs, rdx,wrx, sysclk,rdy frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto tuning ram 0kb/128kb ahb ram 0kb/128kb flex ray clock control flex ray(1ch) rxda - b,txda - b, txena - b, stopwt jtag i/f d a t a s h e e t 56 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? mb91f52 7u , mb91f52 8u from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data external bus i / f peripheral bus bridge can prescaler watchdog timer (sw and hw) delay interrupt interrupt controller rtc / wdt1 calibration / port setting low power consumption setting register 16 32 wild register i / o port debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on chip bus(ahb) xbs clock control (clock setting, main timer, sub timer, pll timer) m p u 32bit peripheral bus (apb) clock control (divide control) bus performance counter 16bit peripheral bus backup ram 16kb timing protection unit ppg (48ch) reload timer (8ch) 8bit da converter (2ch) external interrupt input (16ch) 32bit output compare (6ch) base timer (2ch) u/d counter (2ch) 32bit free - run timer (3ch) 32bit input capture (6ch) multi - function serial interface (12ch) dmac (16 ch) can ( 6 ch) crc operation mode register wave generator (6ch) 12bit ad converter (32ch + 16ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low voltage detection (external power supply low voltage detection) reset control register nmi clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low voltage detection (internal power supply low voltage detection) rstx nmix md0,md1,p006 rx,tx d,a,asx,cs, rdx,wrx, sysclk,rdy frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto flex ray clock control flex ray(1ch) rxda - b,txda - b, txena - b, stopwt flash ? main flash 1600kb/2112kb ? work flash 64kb ram 192kb/192kb on chip bus layer 2 on chip bus layer 1 tuning ram 0kb/128kb ahb ram 0kb/128kb jtag i/f d a t a s h e e t m arch 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 57 confidential ? mb91f52 7m , mb91f52 8m from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data external bus i / f peripheral bus bridge can prescaler watchdog timer (sw and hw) delay interrupt interrupt controller rtc / wdt1 calibration / port setting low power consumption setting register 16 32 wild register i / o port debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on chip bus(ahb) xbs clock control (clock setting, main timer, sub timer, pll timer) m p u 32bit peripheral bus (apb) clock control (divide control) bus performance counter 16bit peripheral bus backup ram 16kb timing protection unit ppg ( 64 ch) reload timer (8ch) 8bit da converter (2ch) external interrupt input ( 24 ch) 32bit output compare ( 8 ch) base timer (2ch) u/d counter ( 4 ch) 32bit free - run timer ( 8 ch) 32bit input capture ( 8 ch) multi - function serial interface ( 20 ch) dmac (16 ch) can ( 6 ch) crc operation mode register wave generator (6ch) 12bit ad converter (32ch + 32 ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low voltage detection (external power supply low voltage detection) reset control register nmi clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low voltage detection (internal power supply low voltage detection) rstx nmix md0,md1,p006 rx,tx d,a,asx,cs, rdx,wrx, sysclk,rdy frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto flex ray clock control flex ray(1ch) rxda - b,txda - b, txena - b, stopwt flash ? main flash 1600kb/2112kb ? work flash 64kb ram 192kb/192kb on chip bus layer 2 on chip bus layer 1 tuning ram 0kb/128kb ahb ram 0kb/128kb jtag i/f d a t a s h e e t 58 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? mb91f52 7y , mb91f52 8y from master to slave from master to slave i / o port xbs crossbar switch fr81s cpu core instruction data external bus i / f peripheral bus bridge can prescaler watchdog timer (sw and hw) delay interrupt interrupt controller rtc / wdt1 calibration / port setting low power consumption setting register 16 32 wild register i / o port debug interface regulator interrupt request batch read dma transfer request generate/clear real time clock clock supervisor on chip bus(ahb) xbs clock control (clock setting, main timer, sub timer, pll timer) m p u 32bit peripheral bus (apb) clock control (divide control) bus performance counter 16bit peripheral bus backup ram 16kb timing protection unit ppg ( 88 ch) reload timer (8ch) 8bit da converter (2ch) external interrupt input ( 24 ch) 32bit output compare ( 8 ch) base timer (2ch) u/d counter ( 4 ch) 32bit free - run timer ( 8 ch) 32bit input capture ( 8 ch) multi - function serial interface ( 20 ch) dmac (16 ch) can ( 6 ch) crc operation mode register wave generator (6ch) 12bit ad converter (32ch + 32 ch) 16bit free - run timer (3ch) 16bit input capture (4ch) power - on reset cr oscillator low voltage detection (external power supply low voltage detection) reset control register nmi clock monitor bus bridge (32bit < - > 16bit) ram ecc control(xbs ram) clock / bus bridge ram ecc control (backup ram) async bus bridge (pclk1 < - > pclk2) bus bridge (32bit < - > 16bit) 16bit output compare (6ch) async bus bridge (pclk1 < - > pclk2) low voltage detection (internal power supply low voltage detection) rstx nmix md0,md1,p006 rx,tx d,a,asx,cs, rdx,wrx, sysclk,rdy frck icu ocu tioa,tiob ain,bin,zin tin,tot dao monclk wot int trg,ppg sout, sin, sck adtg,ain adc enable(ader) icu frck dtti,rto flex ray clock control flex ray(1ch) rxda - b,txda - b, txena - b, stopwt flash ? main flash 1600kb/2112kb ? work flash 64kb ram 192kb/192kb on chip bus layer 2 on chip bus layer 1 tuning ram 0kb/128kb ahb ram 0kb/128kb jtag i/f d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 59 confid ential ? memory map ? mb91f52 7 , mb91f52 8 [ tuning ram function not used ] [ tuning ram function used ] mb91f527 mb91f528 mb91f528 0000 0000 h i/o 0000 0000 h i/o 0000 0000 h i/o 0000 4000 h backup ram(16kb) 0000 4000 h backup ram(16kb) 0000 4000 h backup ram(16kb) 0000 8000 h i/o 0000 8000 h i/o 0000 8000 h i/o 0001 0000 h ram(192kb) 0001 0000 h ram(192kb) 0001 0000 h ram(192kb) 0004 0000 h reserved 0004 0000 h reserved 0004 0000 h reserved 0007 0000 h flash memory 0007 0000 h flash momory 0007 0000 h flash momory (1536+64)kb (2048+64)kb (2048+64)kb 0008 0000 h tuning area (128kb) 000a 0000 h tuning area (128kb) 000c 0000 h 000f fc00 h interrupt vector 000f fc00 h interrupt vector 000f fc00 h interrupt vector reset vector reset vector reset vector 0010 0000 h 0010 0000 h 0010 0000 h 0020 0000 h reserved 0028 0000 h reserved 0028 0000 h reserved 0033 0000 h work flash 0033 0000 h work flash 0033 0000 h work flash (64kb) (64kb) (64kb) 0034 0000 h 0034 0000 h 0034 0000 h reserved reserved reserved 7ffe 0000 h ram 7ffe 0000 h tuning ram (128kb) (128kb) mirror region of tuning area 8000 0000 h 8000 0000 h 8000 0000 h external area external area external area ffff ffff h ffff ffff h ffff ffff h register switching d a t a s h e e t 60 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential ? i/o map the following i/o map shows the relationship between memory space and registers for peripheral resources. legend of i/o map read/write attribute (r: read w: write) address address offset value/ regi ster name block + 0 +1 +2 +3 000090 h bt1tmr[r] h 0000000000000000 bt1tmcr[r/w]b,h,w 00000000 00000000 base timer 1 0000 94 h - bt1stc[r/w] b 00000000 - - 000098 h bt1pcsr/bt1prll[r /w] h 0000000000000000 bt1pdu t/bt1prlh/bt1dtbf[r/w] h 000000000000 0000 00009c h btsel[r/w] b ---- 000 0 - btsssr[w] b,h -------- ------ 11 0000a0 h aderh [r/w]b, h, w 00000000 00000000 aderl [r/w]b, h, w 00000000 00000000 a/d converter 0000a4 h adcs1 [r/w] b, h,w 00000000 adcs0 [r/w] b, h,w 00000000 adcr1 [r] b, h ,w ------ xx adcr0 [r] b, h,w xxxxx xxx 0000a8 h adct1 [r/w] b, h,w 00010000 adct0 [r/w] b, h,w 00101100 adsch [r/w] b, h,w --- 00000 adech [r/w] b, h,w --- 00000 data access attribute b: byte h: half - word w: word (note)the access by the data access attribute not described is disabled. initial register value after reset the initial register value after reset indicates as follows: "1": initial value "1" "0": initial value "0" "x": initial value undefined " - ": reserved bit/undefined bit "*": initia l value "0" or "1" accor d ing to the setting note: the access to addresses not described is disabled. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 61 confidential address address offset value / register name block +0 +1 +2 +3 000000 h pdr00 [r/w] b,h,w xxxxxxxx pdr01 [r/w] b,h,w xxxxxxxx pdr02 [r/w] b,h,w xxxxx xxx pdr03 [r/w] b,h,w xxxxxxxx port data register 000004 h pdr04 [r/w] b,h,w xxxxxxxx pdr05 [r/w] b,h,w xxxxxxxx pdr06 [r/w] b,h,w xxxxxxxx pdr07 [r/w] b,h,w xxxxxxxx 000008 h pdr08 [r/w] b,h,w xxxxxxxx pdr09 [r/w] b,h,w xxxxxxxx pdr10 [r/w] b,h,w xxxxxxx x pdr11 [r/w] b,h,w xxxxxxxx 00000c h pdr12 [r/w] b,h,w xxxxxxxx pdr13 [r/w] b,h,w - xxx -- xx pdr14 [r/w] b,h,w -------- pdr15 [r/w] b,h,w -- xxxxxx 000010 h pdr20 [r/w] b,h,w xxxxxxxx pdr21 [r/w] b,h,w xxxxxxxx pdr22 [r/w] b,h,w xxx -- xxx pdr23 [r/w] b,h,w xxxxxxxx 000014 h pdr24 [r/w] b,h,w -- xxxxxx pdr25 [r/w] b,h,w - xxxxxxx pdr26 [r/w] b,h,w xxxxxx -- pdr27 [r/w] b,h,w xxx - xxxx 000018 h pdr16 [r/w] b,h,w xxxxxxxx pdr17 [r/w] b,h,w xxxxxxxx pdr18 [r/w] b,h,w xxxxxxxx pdr19 [r/w] b,h,w xxxxxxxx 00001c h p dr28 [r/w] b,h,w xxxxxxxx pdr29 [r/w] b,h,w xxxxxxxx D D 000020 h mscy10 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 10,11 32 - bit icu 000024 h mscy11 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000028 h D D msch1011 [r] b,h,w 00000000 mscl1011 [r/w] b,h,w ------ 00 00002c h ipcp10 [r] w xxxxx xxx xxxxxxxx xxxxxxxx xxxxxxxx 000030 h ipcp11 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000034 h D D D ics1011 [r/w] b,h,w 00000000 000038 h wdtecr0 [r/w] b,h,w --- 00000 D D D watchdog timer [s] 00003c h wdtcr0 [r/w] b,h,w - 0 -- 0000 wdtcpr0 [w] b,h,w 00000000 wdtcr1 [r] b,h,w ---- 0110 wdtcpr1 [w] b,h,w 00000000 000040 h D D D D reserved 000044 h dicr [r/w] b ------- 0 D D D delayed interrupt 000048 h to 00005c h D D D D reserved 000060 h tmrlra0 [r/w] h xxxxxxxx xxxxxxxx tmr0 [r] h xxxxxxxx xxxxxxxx r eload timer 0 000064 h tmrlrb0 [r/w] h xxxxxxxx xxxxxxxx tmcsr0 [r/w] b,h,w 00000000 0 - 000000 000068 h tmrlra7 [r/w] h xxxxxxxx xxxxxxxx tmr7 [r] h xxxxxxxx xxxxxxxx reload timer 7 00006c h tmrlrb7 [r/w] h xxxxxxxx xxxxxxxx tmcsr7 [r/w] b,h,w 00000000 0 - 0 00000 000070 h frs8 [r/w] b,h,w - 000 - 000 - 000 - 000 - 000 - 000 - 000 - 000 free - run timer selection register 8 000074 h frs9 [r/w] b,h,w - 000 - 000 - 000 - 000 - 000 - 000 - 000 - 000 free - run timer selection register 9 d a t a s h e e t 62 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 000078 h D D D ocls67 [r/w] b,h,w ---- 0000 ocu67 output level control register 00007c h D D D ocls89 [r/w] b,h,w ---- 0000 ocu89 output level control register 000080 h bt0tmr [r] h 00000000 00000000 bt0tmcr [r/w] h - 000 -- 00 - 000 - 000 base timer 0 000084 h bt0tmcr2 [r/w] b ------- 0 bt0stc [r/w] b - 0 - 0 - 0 - 0 D D 000088 h bt0pcsr/bt0prll [r/w] h 00000000 00000000 bt0pdut/bt0prlh/bt0dtbf [r/w] h 00000000 00000000 00008c h D D D D reserved 000090 h bt1tmr [r] h 00000000 00000000 bt1tmcr [r/w] h - 000 -- 00 - 000 - 000 base tim er 1 000094 h bt1tmcr2 [r/w] b ------- 0 bt1stc [r/w] b - 0 - 0 - 0 - 0 D D 000098 h bt1pcsr/bt1prll [r/w] h 00000000 00000000 bt1pdut/bt1prlh/bt1dtbf [r/w] h 00000000 00000000 00009c h btsel01 [r/w] b ---- 0000 D btsssr [w] b,h -------- ------ 11 base timer 0,1 0000a0 h to 0000fc h D D D D reserved 000100 h tmrlra1 [r/w] h xxxxxxxx xxxxxxxx tmr1 [r] h xxxxxxxx xxxxxxxx reload timer 1 000104 h tmrlrb1 [r/w] h xxxxxxxx xxxxxxxx tmcsr1 [r/w] b, h,w 00000000 0 - 000000 000108 h tmrlra2 [r/w] h xxxxxxxx xxxxxxxx tmr2 [r] h xxxxxxxx xxxxxxxx reload timer 2 00010c h tmrlrb2 [r/w] h xxxxxxxx xxxxxxxx tmcsr2 [r/w] b,h,w 00000000 0 - 000000 000110 h tmrlra3 [r/w] h xxxxxxxx xxxxxxxx tmr3 [r] h xxxxxxxx xxxxxxxx reload timer 3 000114 h tmrlrb3 [r/w] h xxxxxxxx xxxxxxxx tmcsr3 [r /w] b,h,w 00000000 0 - 000000 000118 h mscy4 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 4,5 cycle measurement data register 45 00011c h mscy5 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000120 h occp6 [r/w] w 00000000 00000000 00000000 00000 000 output compare 6,7 32 - bit ocu 000124 h occp7 [r/w] w 00000000 00000000 00000000 00000000 000128 h D D ocsh67 [r/w] b,h,w --- 0 -- 00 ocsl67 [r/w] b,h,w 0000 -- 00 00012c h occp8 [r/w] w 00000000 00000000 00000000 00000000 output compare 8,9 32 - bit ocu 00 0130 h occp9 [r/w] w 00000000 00000000 00000000 00000000 000134 h D D ocsh89 [r/w] b,h,w --- 0 -- 00 ocsl89 [r/w] b,h,w 0000 -- 00 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 63 confidential address address offset value / register name block +0 +1 +2 +3 000138 h occp12 [r/w] w 00000000 00000000 00000000 00000000 output compare 12,13 32 - bit ocu 00013c h occp13 [r/w] w 00000000 0000 0000 00000000 00000000 000140 h D D ocsh1213 [r/w] b,h,w --- 0 -- 00 ocsl1213 [r/w] b,h,w 0000 -- 00 000144 h to 0001b4 h D D D D reserved 0001b8 h epfr64 [r/w] b,h,w ----- 00 - epfr65 [r/w] b,h,w 0000 - 00 - epfr66 [r/w] b,h,w -- 000000 epfr67 [r/w] b,h,w ---- 0 000 extended port function register 0001bc h epfr68 [r/w] b,h,w ---- 0000 epfr69 [r/w] b,h,w ---- 0000 epfr70 [r/w] b,h,w --- 00000 epfr71 [r/w] b,h,w - 0 - 0 - 0 - 0 0001c0 h epfr72 [r/w] b,h,w 000000 - 0 epfr73 [r/w] b,h,w 00000000 epfr74 [r/w] b,h,w 0000000 0 epfr75 [r/w] b,h,w 00000000 0001c4 h epfr76 [r/w] b,h,w 00000 - 0 - epfr77 [r/w] b,h,w -- 000000 epfr78 [r/w] b,h,w ------ 00 epfr79 [r/w] b,h,w 00000000 0001c8 h epfr80 [r/w] b,h,w --- 00000 epfr81 [r/w] b,h,w 00000000 epfr82 [r/w] b,h,w 00000000 ep fr83 [r/w] b,h,w - 0000000 0001cc h epfr84 [r/w] b,h,w 00000000 epfr85 [r/w] b,h,w -- 000000 epfr86 [r/w] b,h,w --- 00000 epfr87 [r/w] b,h,w -------- 0001d0 h epfr88 [r/w] b,h,w ------- 0 epfr89 [r/w] b,h,w - 0 - 00000 epfr90 [r/w] b,h,w - 0 - 0 - 0 - 0 epfr91 [r/w] b,h,w - 0 - 0 - 0 - 0 0001d4 h epfr92 [r/w] b,h,w - 0 - 0 - 0 - 0 epfr93 [r/w] b,h,w 00000000 epfr94 [r/w] b,h,w - 0 - 0 - 0 - 0 epfr95 [r/w] b,h,w - 0 - 0 - 0 - 0 0001d8 h tmrlra4 [r/w] h xxxxxxxx xxxxxxxx tmr4 [r] h xxxxxxxx xxxxxxxx reload timer 4 0001dc h tmrlrb4 [r /w] h xxxxxxxx xxxxxxxx tmcsr4 [r/w] b, h,w 00000000 0 - 000000 0001e0 h epfr96 [r/w] b,h,w - 0 - 0 - 0 - 0 epfr97 [r/w] b,h,w - 0 - 0 - 0 - 0 epfr98 [r/w] b,h,w 0000 - 0 - 0 epfr99 [r/w] b,h,w ---- 0000 extended port function register 0001e4 h epfr100 [r/w] b,h,w ----- 0 0 - epfr101 [r/w] b,h,w ----- 00 - epfr102 [r/w] b,h,w ----- 00 - epfr103 [r/w] b,h,w ----- 00 - 0001e8 h epfr104 [r/w] b,h,w ----- 00 - epfr105 [r/w] b,h,w ----- 00 - epfr106 [r/w] b,h,w ----- 00 - epfr107 [r/w] b,h,w ----- 00 - 0001ec h epfr108 [r/w] b,h,w -- - 00000 epfr109 [r/w] b,h,w -- 000000 epfr110 [r/w] b,h,w -- 000000 epfr111 [r/w] b,h,w ------- 0 0001f0 h tmrlra5 [r/w] h xxxxxxxx xxxxxxxx tmr5 [r] h xxxxxxxx xxxxxxxx reload timer 5 0001f4 h tmrlrb5 [r/w] h xxxxxxxx xxxxxxxx tmcsr5 [r/w] b, h,w 00000000 0 - 000000 d a t a s h e e t 64 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0001f8 h tmrlra6 [r/w] h xxxxxxxx xxxxxxxx tmr6 [r] h xxxxxxxx xxxxxxxx reload timer 6 0001fc h tmrlrb6 [r/w] h xxxxxxxx xxxxxxxx tmcsr6 [r/w] b, h,w 00000000 0 - 000000 000200 h to 000238 h D D D D reserved 00023c h dacr0 [r/w] b,h,w ------- 0 dadr0 [r/w] b,h,w xxxxxxxx dacr1 [r/w] b,h,w ------- 0 dadr1 [r/w] b,h,w xxxxxxxx da converter 000240 h cpclr3 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 3 32 - bit frt 000244 h tcdt3 [r/w] w 00000000 00000000 00000000 00000000 000248 h tccsh3 [r/w] b,h,w 0 ----- 00 tccsl3 [r/w] b,h,w - 1 - 00000 D D 00024c h cpclr4 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 4 32 - bit frt 000250 h tcdt4 [r/w] w 00000000 00000000 00000000 0000000 0 000254 h tccsh4 [r/w] b,h,w 0 ----- 00 tccsl4 [r/w] b,h,w - 1 - 00000 D D 000258 h to 0002c0 h D D D D reserved 0002c4 h to 0002fc h D D D D reserved 000300 h to 00030c h D D D D reserved 000310 h D D mpucr [r/w] h 000000 - 0 ---- 0100 mpu [s] (only cpu core c an access this area) 000314 h D D D D 000318 h D 00031c h D D D 000320 h dpvar [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 65 confidential address address offset value / register name block +0 +1 +2 +3 000324 h D D dpvsr [r/w] h -------- 00000 -- 0 mpu [s] (only cpu core can access this area) 000328 h dear [r] w xxxxxxxx xxxxxxxx xxx xxxxx xxxxxxxx 00032c h D D desr [r/w] h -------- 00000 -- 0 000330 h pabr0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000334 h D D pacr0 [r/w] h 000000 - 0 00000 -- 0 000338 h pabr1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00033c h D D pacr1 [r/w] h 00 0000 - 0 00000 -- 0 000340 h pabr2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000344 h D D pacr2 [r/w] h 000000 - 0 00000 -- 0 000348 h pabr3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 mpu [s] (only cpu core can access this area) 00034c h D D pacr3 [r/w] h 00 0000 - 0 00000 -- 0 000350 h pabr4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 000354 h D D pacr4 [r/w] h 000000 - 0 00000 -- 0 000358 h pabr5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00035c h D D pacr5 [r/w] h 000000 - 0 00000 -- 0 000360 h pabr6 [r/w] w xxxx xxxx xxxxxxxx xxxxxxxx xxxx0000 000364 h D D pacr6 [r/w] h 000000 - 0 00000 -- 0 000368 h pabr7 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxx0000 00036c h D D pacr7 [r/w] h 000000 - 0 00000 -- 0 000370 h to 0003ac h D reserved [s] 0003b0 h to 0003fc h D D D D reserved [s] d a t a s h e e t 66 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 000400 h icsel0 [r/w] b,h,w ----- 000 icsel1 [r/w] b,h,w ---- 0000 icsel2 [r/w] b,h,w ------- 0 icsel3 [r/w] b,h,w ------- 0 dma request generation and clear 000404 h icsel4 [r/w] b,h,w ------- 0 icsel5 [r/w] b,h,w ----- 000 icsel6 [r/w] b,h,w ---- 0000 icse l7 [r/w] b,h,w ---- 0000 000408 h icsel8 [r/w] b,h,w ------ 00 icsel9 [r/w] b,h,w ------ 00 icsel10 [r/w] b,h,w ------ 00 icsel11 [r/w] b,h,w ----- 000 00040c h icsel12 [r/w] b,h,w ------- 0 icsel13 [r/w] b,h,w ------ 00 icsel14 [r/w] b,h,w ------ 00 icsel15 [r/ w] b,h,w ------ 00 000410 h icsel16 [r/w] b,h,w ---- 0000 icsel17 [r/w] b,h,w ------ 00 icsel18 [r/w] b,h,w -- 000000 icsel19 [r/w] b,h,w ----- 000 000414 h icsel20 [r/w] b,h,w ----- 000 icsel21 [r/w] b,h,w ------ 00 icsel22 [r/w] b,h,w ------ 00 icsel23 [r/w] b ,h,w ------ 00 000418 h irpr0h [r] b,h,w 00 ------ irpr0l [r] b,h,w 00 ------ irpr1h [r] b,h,w 00 ------ irpr1l [r] b,h,w 00 ------ interrupt request batch reading register 00041c h D D irpr3h [r] b,h,w 000000 -- irpr3l [r] b,h,w 000000 -- 000420 h irpr4h [r] b,h,w 0000 ---- irpr4l [r] b,h,w 0000 ---- irpr5h [r] b,h,w 0000 ---- irpr5l [r] b,h,w 0000000 - 000424 h irpr6h [r] b,h,w -- 00 ---- irpr6l [r] b,h,w 0000 ---- irpr7h [r] b,h,w - 0 - 00 -- - irpr7l [r] b,h,w ------ 00 000428 h irpr8h [r] b,h,w -- 0 ----- irpr8l [r] b,h,w - 00 ----- irpr9h [r] b,h,w - 0 ------ irpr9l [r] b,h,w - 0 ------ 00042c h irpr10h [r] b,h,w - 0 ------ irpr10l [r] b,h,w - 0 ------ irpr11h [r] b,h,w 0 ------- irpr11l [r] b,h,w 0 ---- --- 000430 h irpr12h [r] b,h,w -- 0000 -- irpr12l [r] b,h,w ---- 00 -- irpr13h [r] b,h,w 00 ------ irpr13l [r] b,h,w 00 ------ interrupt request batch reading register 000434 h irpr14h [r] b,h,w 00000000 irpr14l [r] b,h,w 00000000 irpr15h [r] b,h,w 000 ----- irp r15l [r] b,h,w 00000000 000438 h icsel24 [r/w] b,h,w ------ 00 icsel25 [r/w] b,h,w --- 00000 icsel26 [r/w] b,h,w ------- 0 icsel27 [r/w] b,h,w ------- 0 dma request generation and clear 00043c h irpr16h [r] b,h,w 000 ----- irpr16l [r] b,h,w 00000 --- irpr17h [ r] b,h,w 000 ----- irpr17l [r] b,h,w 000 ----- interrupt request batch reading register d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 67 confidential address address offset value / register name block +0 +1 +2 +3 000440 h icr00 [r/w] b,h,w --- 11111 icr01 [r/w] b,h,w --- 11111 icr02 [r/w] b,h,w --- 11111 icr03 [r/w] b,h,w --- 11111 interrupt controller [s] 000444 h icr04 [r/w] b,h,w - -- 11111 icr05 [r/w] b,h,w --- 11111 icr06 [r/w] b,h,w --- 11111 icr07 [r/w] b,h,w --- 11111 000448 h icr08 [r/w] b,h,w --- 11111 icr09 [r/w] b,h,w --- 11111 icr10 [r/w] b,h,w --- 11111 icr11 [r/w] b,h,w --- 11111 00044c h icr12 [r/w] b,h,w --- 11111 icr13 [r/w] b,h,w --- 11111 icr14 [r/w] b,h,w --- 11111 icr15 [r/w] b,h,w --- 11111 000450 h icr16 [r/w] b,h,w --- 11111 icr17 [r/w] b,h,w --- 11111 icr18 [r/w] b,h,w --- 11111 icr19 [r/w] b,h,w --- 11111 000454 h icr20 [r/w] b,h,w --- 11111 icr21 [r/w] b,h,w --- 11111 icr22 [r/w] b,h,w --- 11111 icr23 [r/w] b,h,w --- 11111 000458 h icr24 [r/w] b,h,w --- 11111 icr25 [r/w] b,h,w --- 11111 icr26 [r/w] b,h,w --- 11111 icr27 [r/w] b,h,w --- 11111 00045c h icr28 [r/w] b,h,w --- 11111 icr29 [r/w] b,h,w --- 11111 icr30 [r/w] b,h,w --- 1111 1 icr31 [r/w] b,h,w --- 11111 000460 h icr32 [r/w] b,h,w --- 11111 icr33 [r/w] b,h,w --- 11111 icr34 [r/w] b,h,w --- 11111 icr35 [r/w] b,h,w --- 11111 000464 h icr36 [r/w] b,h,w --- 11111 icr37 [r/w] b,h,w --- 11111 icr38 [r/w] b,h,w --- 11111 icr39 [r/w] b,h,w --- 11111 000468 h icr40 [r/w] b,h,w --- 11111 icr41 [r/w] b,h,w --- 11111 icr42 [r/w] b,h,w --- 11111 icr43 [r/w] b,h,w --- 11111 00046c h icr44 [r/w] b,h,w --- 11111 icr45 [r/w] b,h,w --- 11111 icr46 [r/w] b,h,w --- 11111 icr47 [r/w] b,h,w --- 11111 000470 h t o 00047c h D D D D reserved [s] 000480 h rstrr [r] b,h,w xxxx -- xx rstcr [r/w] b,h,w 111 ---- 0 stbcr [r/w] b,h,w * 000 --- 11 D reset control [s] power control [s] *: writing stbcr by dma is forbidden 000484 h D D D D reserved [s] 000488 h divr0 [r/w] b,h,w 000 ----- d ivr1 [r/w] b,h,w 0001 ---- divr2 [r/w] b,h,w 0011 ---- D clock control [s] 00048c h D D D D reserved [s] 000490 h iorr0 [r/w] b,h,w - 0000000 iorr1 [r/w] b,h,w - 0000000 iorr2 [r/w] b,h,w - 0000000 iorr3 [r/w] b,h,w - 0000000 dma request by peripheral [s] 00049 4 h iorr4 [r/w] b,h,w - 0000000 iorr5 [r/w] b,h,w - 0000000 iorr6 [r/w] b,h,w - 0000000 iorr7 [r/w] b,h,w - 0000000 000498 h iorr8 [r/w] b,h,w - 0000000 iorr9 [r/w] b,h,w - 0000000 iorr10 [r/w] b,h,w - 0000000 iorr11 [r/w] b,h,w - 0000000 00049c h iorr12 [r/w] b, h,w - 0000000 iorr13 [r/w] b,h,w - 0000000 iorr14 [r/w] b,h,w - 0000000 iorr15 [r/w] b,h,w - 0000000 0004a0 h D D D D reserved 0004a4 h canpre [r/w] b,h,w --- 00000 D D D can prescaler 0004a8 h D D cscfg[r/w]b,h,w --- 0 ---- cmcfg[r/w]b,h,w 00000000 clock monitor control register 0004ac h aderh0[r/w] b,h 11111111 11111111 aderl0[r/w] b,h 11111111 11111111 analog inp ut control register 0 0004b0 h aderh1[r/w] b,h 11111111 11111111 aderl1[r/w] b,h 11111111 11111111 analog input control register 1 d a t a s h e e t 68 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0004b4 h D D D D reserved 0004b8 h cucr0 [r/w] b,h,w -------- --- 0 -- 00 cutd0 [r/w] b,h,w 10000000 00000000 rtc/wdt1 calibrati on 0004bc h cutr0 [r] b,h,w -------- 00000000 00000000 00000000 0004c0 h D D D D 0004c4 h cucr1 [r/w] b,h,w -------- --- 0 -- 00 cutd1 [r/w] b,h,w 11000011 01010000 0004c8 h cutr1 [r] b,h,w -------- 00000000 00000000 00000000 0004cc h D D D D reserved 0 004d0 h pll2divm[r/w] b,h,w ---- 0000 pll2divn[r/w] b,h,w - 0000000 pll2divg[r/w] b,h,w ---- 0000 pll2mulg[r/w] b,h,w 00000000 clock control for flexray 0004d4 h pll2ctrl[r/w] b,h,w ---- 0000 pll2divk[r/w] b,h,w ------- 0 clkr2[r/w] b,h,w 000 -- 000 D 000 4d8 h icsel28 [r/w] b,h,w ------- 0 icsel29 [r/w] b,h,w ------- 0 icsel30 [r/w] b,h,w ------- 0 icsel31 [r/w] b,h,w ------- 0 dma request generation and clear 0004dc h icsel32 [r/w] b,h,w ------- 0 icsel33 [r/w] b,h,w ------- 0 D D 0004e0 h to 00050c h D D D D re served 000510 h cselr [r/w] b,h,w 001 --- 00 cmonr [r] b,h,w 001 --- 00 mtmcr [r/w] b,h,w 00001111 stmcr [r/w] b,h,w 0000 - 111 clock control [s] 000514 h pllcr [r/w] b,h,w -------- 11110000 cstbr [r/w] b,h,w - 0000000 ptmcr [r/w] b,h,w 00 ------ 000518 h D D cpu ar [r/w] b,h,w 0 ---- xxx D reset control [s] 00051c h D D D D reserved [s] 000520 h ccpsselr [r/w] b,h,w ------- 0 D D ccpsdivr [r/w] b,h,w - 000 - 000 clock control 2 [s] 000524 h D ccpllfbr [r/w] b,h,w - 0000000 ccssfbr0 [r/w] b,h,w -- 000000 ccssfbr1 [r/w] b,h,w --- 00000 000528 h D ccssccr0 [r/w] b,h,w ---- 0000 ccssccr1 [r/w] h,w 000 ----- -------- 00052c h D cccgrcr0 [r/w] b,h,w 00 ---- 00 cccgrcr1 [r/w] b,h,w 00000000 cccgrcr2 [r/w] b,h,w 00000000 000530 h ccrtselr [r/w] b,h,w 0 ------ 0 D ccpmucr0 [r /w] b,h,w 0 ----- 00 ccpmucr1 [r/w] b,h,w 0 -- 00000 clock control 2 [s] 000534 h to 00053c h D D D D reserved d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 69 confidential address address offset value / register name block +0 +1 +2 +3 000540 h eirr2 [r/w] b,h,w xxxxxxxx enir2 [r/w] b,h,w 00000000 elvr2 [r/w] b,h,w 00000000 00000000 external interrupt (int16 to 23) 000544 h to 0005 4c h D D D D reserved 000550 h eirr0 [r/w] b,h,w xxxxxxxx enir0 [r/w] b,h,w 00000000 elvr0 [r/w] b,h,w 00000000 00000000 external interrupt (int0 to 7) 000554 h eirr1 [r/w] b,h,w xxxxxxxx enir1 [r/w] b,h,w 00000000 elvr1 [r/w] b,h,w 00000000 00000000 extern al interrupt (int8 to 15) 000558 h D D D D reserved 00055c h D D wtdr [r/w] h 00000000 00000000 real time clock (rtc) 000560 h D wtcrh [r/w] b ------ 00 wtcrm [r/w] b,h 00000000 wtcrl [r/w] b,h ---- 00 - 0 000564 h D wtbrh [r/w] b -- xxxxxx wtbrm [r/w] b xxxxx xxx wtbrl [r/w] b xxxxxxxx 000568 h wthr [r/w] b,h --- 00000 wtmr [r/w] b,h -- 000000 wtsr [r/w] b -- 000000 D 00056c h D csvcr [r/w] b 000111 -- D D clock supervisor 000570 h to 00057c h D D D D reserved 000580 h regsel [r/w] b,h,w 0110011 - D D D regulator control / low voltage detection 000584 h lvd5r [r/w] b,h,w ------- 1 lvd5f [r/w] b,h,w 00000001 lvd [r/w] b,h,w 01000 -- 0 D 000588 h , 00058c h D D D D reserved 000590 h pmustr [r/w] b,h,w 0 ----- 1x pmuctlr [r/w] b,h,w 0 - 00 ---- pwrtmctl [r/w] b,h,w ----- 011 D pmu 000594 h pmuintf0 [r/w] b,h,w 00000000 pmuintf1 [r/w] b,h,w 00000000 pmuintf2 [r/w] b,h,w 0000 ---- pmuintf3 [r/w] b,h,w 00000000 pmu 000598 h D D D D 00059c h to 0005fc h D D D D reserved 000600 h asr0 [r/w] w 00000000 00000000 -------- 1111 - 001 external bus interface [s] 000604 h asr1 [r/w] w xxxxxxxx xxxxxxxx -------- xxxx - xx0 000608 h asr2 [r/w] w xxxxxxxx xxxxxxxx -------- xxxx - xx0 00060c h asr3 [r/w] w xxxxxxxx xxxxxxxx -------- xxxx - xx0 external bus interface [s] 000610 h to 00063c h D D D D reserved [s] d a t a s h e e t 70 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 000640 h acr0 [r/w] w -------- -------- -------- 01 -- 00 -- external bus interface [s] 000644 h acr1 [r/w] w -------- -------- -------- xx -- xx -- 000648 h acr2 [r/w] w -------- -------- -------- xx -- xx -- 00064c h acr3 [r/w] w -------- --- ----- -------- xx -- xx -- 000650 h to 00067c h D D D D reserved [s] 000680 h awr0 [r/w] w ---- 1111 00000000 11110000 00000 - 0 - external bus interface [s] 000684 h awr1 [r/w] w ---- xxxx xxxxxxxx xxxxxxxx xxxxx - x - 000688 h awr2 [r/w] w ---- xxxx xxxxxxxx xxxxxx xx xxxxx - x - 00068c h awr3 [r/w] w ---- xxxx xxxxxxxx xxxxxxxx xxxxx - x - 000690 h to 0006fc h D D D D reserved [s] 000700 h to 00070c h D D D D reserved 000710 h bpccra [r/w] b 00000000 bpccrb [r/w] b 00000000 bpccrc [r/w] b 00000000 D bus performance counter 000714 h bpctra [r/w] w 00000000 00000000 00000000 00000000 000718 h bpctrb [r/w] w 00000000 00000000 00000000 00000000 00071c h bpctrc [r/w] w 00000000 00000000 00000000 00000000 000720 h to 0007f8 h D D D D reserved 0007fc h bmodr [r] b, h, w xxxxxxx x D D D mode register 000800 h to 00083c h D D D D reserved [s] 000840 h fctlr [r/w] h - 0 -- 1000 0 -- 0 ---- D fstr [r/w] b ----- 001 flash memory register [s] 000844 h to 000854 h D D D D reserved [s] 000858 h D D wren [r/w] h 00000000 00000000 wild register [s] 00085c h to 00087c h D D D D reserved [s] d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 71 confidential address address offset value / register name block +0 +1 +2 +3 000880 h wrar00 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [s] 000884 h wrdr00 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000888 h wrar01 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00088c h wrdr 01 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000890 h wrar02 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 000894 h wrdr02 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000898 h wrar03 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 00089c h wrdr03 [r/w] w x xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a0 h wrar04 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008a4 h wrdr04 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008a8 h wrar05 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008ac h wrdr05 [r/w] w xxxxxxxx xxxx xxxx xxxxxxxx xxxxxxxx 0008b0 h wrar06 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008b4 h wrdr06 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008b8 h wrar07 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008bc h wrdr07 [r/w] w xxxxxxxx xxxxxxxx xxxxxxx x xxxxxxxx 0008c0 h wrar08 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008c4 h wrdr08 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008c8 h wrar09 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008cc h wrdr09 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008d0 h wrar10 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008d4 h wrdr10 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008d8 h wrar11 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008dc h wrdr11 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx d a t a s h e e t 72 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0008e0 h wra r12 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- wild register [s] 0008e4 h wrdr12 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008e8 h wrar13 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008ec h wrdr13 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f0 h wrar14 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008f4 h wrdr14 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0008f8 h wrar15 [r/w] w -------- -- xxxxxx xxxxxxxx xxxxxx -- 0008fc h wrdr15 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000900 h tpuunlock [r/w] w 00000000 00000000 00000000 00000000 time protection unit [s] 000904 h tpulst [r] b,h,w ------- 0 D tpuvst [r/w] b,h,w ----- 000 D 000908 h tpucfg [r/w] b,h,w ------- 0 0 - 000000 -------- ------- 0 00090c h tputir [r] b,h,w 00000000 D D D 000910 h tputst [r] b,h,w 00000000 D D D 000914 h tputie [r/w] b,h,w 00000000 D D D 000918 h tputmid [r] b,h,w 000 00000 00000000 00000000 00000000 00091c h to 00092c h D D D D 000930 h tputcn00 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000934 h tputcn01 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000938 h tputcn02 [r/w] b,h,w 000000 -- 00000000 00000000 0 0000000 00093c h tputcn03 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000940 h tputcn04 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000944 h tputcn05 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 000948 h tputcn06 [r/w] b,h,w 000000 -- 0000000 0 00000000 00000000 00094c h tputcn07 [r/w] b,h,w 000000 -- 00000000 00000000 00000000 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 73 confidential address address offset value / register name block +0 +1 +2 +3 000950 h tputcn10 [r/w] b,h,w --- 00000 D D D time protection unit [s] 000954 h tputcn11 [r/w] b,h,w --- 00000 D D D 000958 h tputcn12 [r/w] b,h,w --- 00000 D D D 00095c h tputcn13 [r/w] b,h,w --- 00000 D D D 000960 h tputcn14 [r/w] b,h,w --- 00000 D D D 000964 h tputcn15 [r/w] b,h,w --- 000 00 D D D 000968 h tputcn16 [r/w] b,h,w --- 00000 D D D 00096c h tputcn17 [r/w] b,h,w --- 00000 D D D 000970 h tputcc0 [r] b,h,w -------- 00000000 00000000 00000000 000974 h tputcc1 [r] b,h,w -------- 00000000 00000000 00000000 000978 h tputcc2 [r] b,h ,w -------- 00000000 00000000 00000000 00097c h tputcc3 [r] b,h,w -------- 00000000 00000000 00000000 000980 h tputcc4 [r] b,h,w -------- 00000000 00000000 00000000 000984 h tputcc5 [r] b,h,w -------- 00000000 00000000 00000000 000988 h tputcc6 [r] b,h ,w -------- 00000000 00000000 00000000 00098c h tputcc7 [r] b,h,w -------- 00000000 00000000 00000000 000990 h to 0009fc h D D D D 000a00 h to 000bec h D D D D reserved 000bf0 h hscfr [r/w] b,h,w -------- ------ 00 00000000 00000000 ocdu 000bf4 h D D D D 000bf8 h D D mbr [r/w] b,h,w 00 ------ xxxxxxxx 000bfc h D D uer [w] b,h,w -------- ------- x d a t a s h e e t 74 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 000c00 h dccr0 [r/w] w 0 ---- 0 00 -- 00 -- 00 00000000 0 - 000000 dma controller [s] 000c04 h dcsr0 [r/w] h 0 ------- ----- 000 dtcr0 [r/w] h 00000000 00000000 000c08 h dsar0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c0c h ddar0 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c14 h dcsr 1 [r/w] h 0 ------- ----- 000 dtcr1 [r/w] h 00000000 00000000 000c18 h dsar1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c1c h ddar1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c20 h dccr2 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c24 h dcsr2 [r/w] h 0 ------- ----- 000 dtcr2 [r/w] h 00000000 00000000 000c28 h dsar2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c2c h ddar2 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c30 h dccr3 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c34 h dcsr3 [r /w] h 0 ------- ----- 000 dtcr3 [r/w] h 00000000 00000000 000c38 h dsar3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c3c h ddar3 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c40 h dccr4 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c44 h dcsr4 [r/ w] h 0 ------- ----- 000 dtcr4 [r/w] h 00000000 00000000 000c48 h dsar4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c4c h ddar4 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c50 h dccr5 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c54 h dcsr5 [r/w] h 0 ------- ----- 000 dtcr5 [r/w] h 00000000 00000000 000c58 h dsar5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c5c h ddar5 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 75 confidential address address offset value / register name block +0 +1 +2 +3 000c60 h dccr6 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 dma controller [s] 000 c64 h dcsr6 [r/w] h 0 ------- ----- 000 dtcr6 [r/w] h 00000000 00000000 000c68 h dsar6 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c6c h ddar6 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c70 h dccr7 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c7 4 h dcsr7 [r/w] h 0 ------- ----- 000 dtcr7 [r/w] h 00000000 00000000 000c78 h dsar7 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c7c h ddar7 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c80 h dccr8 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c84 h dcsr8 [r/w] h 0 ------- ----- 000 dtcr8 [r/w] h 00000000 00000000 000c88 h dsar8 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c8c h ddar8 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c90 h dccr9 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000c94 h dcsr9 [r/w] h 0 ------- ----- 000 dtcr9 [r/w] h 00000000 00000000 000c98 h dsar9 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000c9c h ddar9 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ca0 h dccr10 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000ca4 h d csr10 [r/w] h 0 ------- ----- 000 dtcr10 [r/w] h 00000000 00000000 000ca8 h dsar10 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cac h ddar10 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cb0 h dccr11 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cb4 h dcsr11 [r/w] h 0 ------- ----- 000 dtcr11 [r/w] h 00000000 00000000 000cb8 h dsar11 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cbc h ddar11 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx d a t a s h e e t 76 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 000cc0 h dccr12 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 dma controller [s] 000cc4 h dcsr12 [r/w] h 0 ------- ----- 000 dtcr12 [r/w] h 00000000 00000000 000cc8 h dsar12 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ccc h ddar12 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cd0 h dccr13 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000cd4 h dcsr13 [r/w] h 0 ------- ----- 000 dtcr13 [r/w] h 00000000 00000000 000cd8 h dsar13 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cdc h ddar13 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ce0 h dccr14 [r/w] w 0 ---- 000 -- 00 -- 00 00000000 0 - 000000 000ce4 h dcsr14 [r/w] h 0 ------- ----- 000 dtcr14 [r/w] h 00000000 00000000 000ce8 h dsar14 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cec h ddar14 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cf0 h dccr15 [r/w] w 0 ---- 000 - - 00 -- 00 00000000 0 - 000000 000cf4 h dcsr15 [r/w] h 0 ------- ----- 000 dtcr15 [r/w] h 00000000 00000000 000cf8 h dsar15 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000cfc h ddar15 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000d00 h to 000df0 h D D D D reserved [s] 000df4 h D D dnmir [r/w] b 0 ------ 0 dilvr [r/w] b --- 11111 dma controller [s] 000df8 h dmacr[r/w] w 0 ------- -------- 0 ------- -------- 000dfc h D D D D reserved [s] d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 77 confidential address address offset value / register name block +0 +1 +2 +3 000e00 h ddr00 [r/w] b,h,w 00000000 ddr01 [r/w] b,h,w 00000000 ddr02 [r/w] b,h,w 00000000 ddr03 [r/w] b,h,w 00000000 data direction register 000e04 h ddr04 [r/w] b,h,w 00000000 ddr05 [r/w] b,h,w 00000000 ddr06 [r/w] b,h,w 00000000 ddr07 [r/w] b,h,w 00000000 000e08 h ddr08 [r/w] b,h,w 00000000 ddr09 [r/w] b,h,w 00000000 dd r10 [r/w] b,h,w 00000000 ddr11 [r/w] b,h,w 00000000 000e0c h ddr12 [r/w] b,h,w 00000000 ddr13 [r/w] b,h,w - 000 -- 00 ddr14 [r/w] b,h,w -------- ddr15 [r/w] b,h,w -- 000000 000e10 h ddr20 [r/w] b,h,w 00000000 ddr21 [r/w] b,h,w 00000000 ddr22 [r/w] b,h,w 000 - - 000 ddr23 [r/w] b,h,w 00000000 000e14 h ddr24 [r/w] b,h,w -- 000000 ddr25 [r/w] b,h,w - 0000000 ddr26 [r/w] b,h,w 000000 -- ddr27 [r/w] b,h,w 000 - 0000 000e18 h ddr16 [r/w] b,h,w 00000000 ddr17 [r/w] b,h,w 00000000 ddr18 [r/w] b,h,w 00000000 ddr19 [r/w] b,h ,w 00000000 000e1c h ddr28 [r/w] b,h,w 00000000 ddr29 [r/w] b,h,w 00000000 D D 000e20 h pfr00 [r/w] b,h,w 00000000 pfr01 [r/w] b,h,w 00000000 pfr02 [r/w] b,h,w 00000000 pfr03 [r/w] b,h,w 00000000 port function register 000e24 h pfr04 [r/w] b,h,w 00000000 pfr05 [r/w] b,h,w 00000000 pfr06 [r/w] b,h,w 00000000 pfr07 [r/w] b,h,w 000 00000 000e28 h pfr08 [r/w] b,h,w 00000000 pfr09 [r/w] b,h,w 00000000 pfr10 [r/w] b,h,w 00000000 pfr11 [r/w] b,h,w 00000000 000e2c h pfr12 [r/w] b,h,w 00000000 pfr13 [r/w] b,h,w - 000 -- 00 pfr14 [r/w] b,h,w -------- pfr15 [r/w] b,h,w -- 000000 000e30 h pfr2 0 [r/w] b,h,w 00000000 pfr21 [r/w] b,h,w 00000000 pfr22 [r/w] b,h,w 000 -- 000 pfr23 [r/w] b,h,w 00000000 000e34 h pfr24 [r/w] b,h,w -- 000000 pfr25 [r/w] b,h,w - 0000000 pfr26 [r/w] b,h,w 000000 -- pfr27 [r/w] b,h,w 000 - 0000 000e38 h pfr16 [r/w] b,h,w 000000 00 pfr17 [r/w] b,h,w 00000000 pfr18 [r/w] b,h,w 00000000 pfr19 [r/w] b,h,w 00000000 000e3c h pfr28 [r/w] b,h,w 00000000 pfr29 [r/w] b,h,w 00000000 D D 000e40 h pddr00 [r] b,h,w xxxxxxxx pddr01 [r] b,h,w xxxxxxxx pddr02 [r] b,h,w xxxxxxxx pddr03 [r] b,h,w xxxxxxxx port direct read register 000e44 h pddr04 [r] b,h,w xxxxxxxx pddr05 [r] b,h,w xxxxxxxx pddr06 [r] b,h,w xxxxxxxx pddr07 [r] b,h,w xxxxxxxx 000e48 h pddr08 [r] b,h,w xxxxxxxx pddr09 [r] b,h,w xxxxxxxx pddr10 [r] b,h,w xxxxxxxx pddr11 [r] b,h,w xx xxxxxx 000e4c h pddr12 [r] b,h,w xxxxxxxx pddr13 [r] b,h,w - xxx -- xx pddr14 [r] b,h,w -------- pddr15 [r] b,h,w -- xxxxxx 000e50 h pddr20 [r] b,h,w xxxxxxxx pddr21 [r] b,h,w xxxxxxxx pddr22 [r] b,h,w xxx -- xxx pddr23 [r] b,h,w xxxxxxxx 000e54 h pddr24 [r] b,h,w -- xxxxxx pddr25 [r] b,h,w - xxxxxxx pddr26 [r] b,h,w xxxxxx -- pddr27 [r] b,h,w xxx - xxxx 000e58 h pddr16 [r] b,h,w xxxxxxxx pddr17 [r] b,h,w xxxxxxxx pddr18 [r] b,h,w xxxxxxxx pddr19 [r] b,h,w xxxxxxxx 000e5c h pddr28 [r] b,h,w xxxxxxxx pddr29 [r] b, h,w xxxxxxxx D D 000e60 h epfr00 [r/w] b,h,w 00000000 epfr01 [r/w] b,h,w - 0 - 0 - 000 epfr02 [r/w] b,h,w ---- 0000 epfr03 [r/w] b,h,w --- 000 - 0 extended port function register 000e64 h epfr04 [r/w] b,h,w ---- 00 - 0 epfr05 [r/w] b,h,w ---- 0000 epfr06 [r/w] b,h,w ---- 000 - epfr07 [r/w] b,h,w --- 00000 d a t a s h e e t 78 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 000e68 h epfr08 [r/w] b,h,w --- 00000 epfr09 [r/w] b,h,w ----- 00 - epfr10 [r/w] b,h,w ---- 0000 epfr11 [r/w] b,h,w ---- 0000 extended port function register 000e6c h epfr12 [r/w] b,h,w ---- 0000 epfr13 [r/w] b,h,w ------ 00 epfr14 [r/w] b,h,w ------ 00 epfr15 [r/w] b,h,w ----- 000 000e70 h D D D D 000e74 h D D D D 000e78 h D D epfr26 [r/w] b,h,w 00000000 epfr27 [r/w] b,h,w --- 0 ---- 000e7c h epfr28 [r/w] b,h,w -- 000 - 0 - epfr29 [r/w] b,h,w 00000000 D D 000e80 h D epfr33 [r/w] b,h,w ----- 00 - epfr34 [r/w] b,h,w ----- 00 - epfr35 [r/w] b, h,w --- 00000 000e84 h epfr36 [r/w] b,h,w ---- 0 - 0 - D D D 000e88 h D D epfr42 [r/w] b,h,w ------ 00 epfr43 [r/w] b,h,w 0 -- 0000 - 000e8c h epfr44 [r/w] b,h,w - 00 --- 0 - epfr45 [r/w] b,h,w - 0000000 D D 000e90 h epfr48 [r/w] b,h,w ----- 0 - 0 epfr49 [r/w] b ,h,w ----- 000 epfr50 [r/w] b,h,w ------ 00 epfr51 [r/w] b,h,w --- 00000 000e94 h D D D D 000e98 h epfr56 [r/w] b,h,w ----- 0 - 0 epfr57 [r/w] b,h,w ----- 0 - 0 epfr58 [r/w] b,h,w ---- 00 - 0 epfr59 [r/w] b,h,w ---- 00 - 0 000e9c h epfr60 [r/w] b,h,w ---- 00 -- e pfr61 [r/w] b,h,w ----- 00 - epfr62 [r/w] b,h,w ----- 00 - epfr63 [r/w] b,h,w --- 0 - 0 -- 000ea0 h to 000eb0 h D D D D reserved 000eb4 h cpclr9 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 9 32 - bit frt 000eb8 h tcdt9 [r/w] w 00000000 00000000 000 00000 00000000 000ebc h tccsh9 [r/w] b,h,w 0 ----- 00 tccsl9 [r/w] b,h,w - 1 - 00000 D D 000ec0 h pper00 [r/w] b,h,w 00000000 pper01 [r/w] b,h,w 00000000 pper02 [r/w] b,h,w 00000000 pper03 [r/w] b,h,w 00000000 port pull - up/down enable register 000ec4 h pper04 [r/w] b,h,w 00000000 pper05 [r/w] b,h,w 00000000 pper06 [r/w] b,h,w 00000000 pper07 [r/w] b,h,w 00000000 000ec8 h pper08 [r/w] b,h,w 00000000 pper09 [r/w] b,h,w 00000000 pper10 [r/w] b,h,w 00000000 pper11 [r/w] b,h,w 00000000 000ecc h pper12 [r/w] b,h,w 00000000 pper13 [r/w] b,h,w - 000 -- 00 pper14 [r/w] b,h,w -------- pper15 [r/w] b,h,w -- 000000 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 79 confidential address address offset value / register name block +0 +1 +2 +3 000ed0 h pper20 [r/w] b,h,w 00000000 pper21 [r/w] b,h,w 00000000 pper22 [r/w] b,h,w 000 -- 000 pper23 [r/w] b,h,w 00000000 port pull - up/down enable register 000ed 4 h pper24 [r/w] b,h,w -- 000000 pper25 [r/w] b,h,w - 0000000 pper26 [r/w] b,h,w 000000 -- pper27 [r/w] b,h,w 000 - 0000 000ed8 h pper16 [r/w] b,h,w 00000000 pper17 [r/w] b,h,w 00000000 pper18 [r/w] b,h,w 00000000 pper19 [r/w] b,h,w 00000000 000edc h pper28 [r /w] b,h,w 00000000 pper29 [r/w] b,h,w 00000000 D D 000ee0 h pilr00[r/w] b,h,w 11 - 1 -- 1 - pilr01[r/w] b,h,w 11111111 D D port input level register 000ee4 h D pilr05[r/w] b,h,w ----- 1 -- D D 000ee8 h D D D pilr11[r/w] b,h,w --- 1 ---- 000eec h pilr12[r/w] b,h,w ---- 1 -- 1 D D pilr15[r/w] b,h,w -- 1 ----- 000 ef0 h cpclr10 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 10 32 - bit frt 000ef4 h tcdt10 [r/w] w 00000000 00000000 00000000 00000000 000ef8 h tccsh10 [r/w] b,h,w 0 ----- 00 tccsl10 [r/w] b,h,w - 1 - 00000 D D 000efc h to 000f0c h D D D D reserved 000f10 h rcrh2 [r/w] h,w xxxxxxxx rcrl2 [r/w] b,h,w xxxxxxxx udcrh2 [r/w] h,w 00000000 udcrl2 [r/w] b,h,w 00000000 updown counter 2 000f14 h ccr2 [r/w] b,h 00000000 - 0001000 D csr2 [r/w] b 00000000 000f18 h rcrh3 [r/w] h,w xxxxxxxx rcrl3 [r/w] b,h,w xxxxx xxx udcrh3 [r/w] h,w 00000000 udcrl3 [r/w] b,h,w 00000000 updown counter 3 000f1c h ccr3 [r/w] b,h 00000000 - 0001000 D csr3 [r/w] b 00000000 000f20 h to 000f30 h D D D D reserved 000f34 h , 000f38 h D D D D reserved 000f3c h D D D ocls1213 [r/w] b,h,w ---- 00 00 ocu12,13 output level control register 000f40 h porten [r/w] b,h,w ------- 0 D D D port enable register 000f44 h keycdr [r/w] h 00000000 00000000 D D keycoderegister 000f48 h to 000f64 h D D D D reserved d a t a s h e e t 80 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 000f68 h mscy6 [r] h,w xxxxxxxx xxxxxxxx xxxxxx xx xxxxxxxx input capture 6,7 cycle measurement data register 67 000f6c h mscy7 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000f70 h rcrh0 [w] h,w xxxxxxxx rcrl0 [w] b,h,w xxxxxxxx udcrh0 [r] h,w 00000000 udcrl0 [r] b,h,w 00000000 updown counter 0 000f74 h ccr0 [r/w] b,h 00000000 - 0001000 D csr0 [r/w] b 00000000 000f78 h , 000f7c h D D D D reserved 000f80 h rcrh1 [w] h,w xxxxxxxx rcrl1 [w] b,h,w xxxxxxxx udcrh1 [r] h,w 00000000 udcrl1 [r] b,h,w 00000000 updown counter 1 000f84 h ccr1 [r/w] b,h 00000000 - 0001000 D csr1 [r/w] b 00000000 000f 88 h D D msch45 [r] b,h,w 00000000 mscl45 [r/w] b,h,w ------ 00 input capture 4,5 32 - bit icu cycle and pulse width measurement control 45 000f8c h D D msch67 [r] b,h,w 00000000 mscl67 [r/w] b,h,w ------ 00 input capture 6,7 32 - bit icu cycle and pulse wid th measurement control 67 000f90 h occp10 [r/w] w 00000000 00000000 00000000 00000000 output compare 10,11 32 - bit ocu 000f94 h occp11 [r/w] w 00000000 00000000 00000000 00000000 000f98 h D D ocsh1011 [r/w] b,h,w --- 0 -- 00 ocsl1011 [r/w] b,h,w 0000 -- 00 000f9c h D D D ocls1011 [r/w] b,h,w ---- 0000 ocu10,11 output level control register 000fa0 h cpclr5 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 5 32 - bit frt 000fa4 h tcdt5 [r/w] w 00000000 00000000 00000000 00000000 000fa8 h tccsh5 [r/w]b, h,w 0 ----- 00 tccsl5 [r/w]b,h,w - 1 - 00000 D D 000fac h cpclr6 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 6 32 - bit frt 000fb0 h tcdt6 [r/w] w 00000000 00000000 00000000 00000000 000fb4 h tccsh6 [r/w]b,h,w 0 ----- 00 tccsl6 [r/w]b,h,w - 1 - 00000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 81 confidential address address offset value / register name block +0 +1 +2 +3 000fb8 h cpclr7 [r/w] w 11111111 11111111 11111111 11111111 free - run timer 7 32 - bit frt 000fbc h tcdt7 [r/w] w 00000000 00000000 00000000 00000000 000fc0 h tccsh7 [r/w]b,h,w 0 ----- 00 tccsl7 [r/w]b,h,w - 1 - 00000 D D 000fc4 h cpclr8 [r/w] w 11111111 1 1111111 11111111 11111111 free - run timer 8 32 - bit frt 000fc8 h tcdt8 [r/w] w 00000000 00000000 00000000 00000000 000fcc h tccsh8 [r/w]b,h,w 0 ----- 00 tccsl8 [r/w]b,h,w - 1 - 00000 D D 000fd0 h ipcp4 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 4,5 32 - bit icu 000fd4 h ipcp5 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000fd8 h D lsyns2 [r/w] b,h,w -- 000000 lsyns1 [r/w] b,h,w 00000000 ics45 [r/w] b,h,w 00000000 000fdc h ipcp6 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 6,7 32 - bit icu 000f e0 h ipcp7 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000fe4 h D D D ics67 [r/w] b,h,w 00000000 000fe8 h ipcp8 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx input capture 8,9 32 - bit icu 000fec h ipcp9 [r] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ff0 h D D D i cs89 [r/w] b,h,w 00000000 000ff4 h mscy8 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ff8 h mscy9 [r] h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000ffc h D D msch89 [r] b,h,w 00000000 mscl89 [r/w] b,h,w ------ 00 001000 h sacr [r/w] b,h,w ------- 0 picd [ r/w] b,h,w ---- 0011 D D clock control 001004 h to 00112c h D D D D reserved 001130 h D D D crccr [r/w] b,h,w - 0000000 crc calculation unit 001134 h crcinit [r/w] b,h,w 11111111 11111111 11111111 11111111 001138 h crcin [r/w] b,h,w 00000000 00000000 0000000 0 00000000 00113c h crcr [r] b,h,w 11111111 11111111 11111111 11111111 d a t a s h e e t 82 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001140 h scr16/(ibcr16) [r/w] b,h,w 0 -- 00000 smr16 [r/w] b,h,w 000 - 00 - 0 ssr16 [r/w] b,h,w 0 - 000011 escr16/(ibsr16) [r/w] b,h,w 00000000 multi - uart16 *1: byte access is possible only f or access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 001144 h D /(rdr116/(tdr116))[r/w] b,h,w -------- -------- * 3 rdr016/(tdr016)[r/w] b,h,w ------- 0 00000000* 1 001148 h sacsr16[r/w] b,h,w 0 ---- 000 00000000 stmr16[r] b,h,w 00000000 00000000 00114c h stmcr16[r/w] b,h,w 00000000 00000000 D /(scscr16/sfur16)[r/w] b,h, w -------- -------- * 3 * 4 001150 h D /(scstr316)/ (lamsr16) [r/w] b,h,w -------- * 3 D /(scstr216)/ (lamcr16) [r/w] b,h,w -------- * 3 D /(scstr116)/(sflr11 6) [r/w] b,h,w -------- * 3 D /(scstr016)/(sflr01 6) [r/w] b,h,w -------- * 3 001154 h D D /(scsfr216) [r/w] b,h,w -------- * 3 D /(scsfr116) [r/w] b,h,w -------- * 3 D /(scsfr016) [r/w] b,h,w -------- * 3 001158 h D/(tbyte316)/ (lamesr16) [r/w] b,h,w -------- * 3 D/(tbyte216)/ (lamert16) [r/w] b,h,w -------- * 3 D/(tbyte116)/ (lamier16) [r/w] b,h,w -------- * 3 tbyte016/( lamrid 16)/(lamtid16) [r/w] b,h,w 00000000 00115c h bgr16[r/w] h,w 00000000 00000000 D /(ismk16) [r/w] b,h,w -------- * 2 D /(isba16) [r/w] b,h,w -------- * 2 001160 h fcr116 [r/w] b,h,w --- 00100 fcr016 [r/w] b,h,w - 0000000 fbyte16[r/w] b,h,w 00000000 0000000 0 001164 h fticr16[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 83 confidential address address offset value / register name block +0 +1 +2 +3 001168 h scr17/(ibcr17) [r/w] b,h,w 0 -- 00000 smr17 [r/w] b,h,w 000 - 00 - 0 ssr17 [r/w] b,h,w 0 - 000011 escr17/(ibsr17) [r/w] b,h,w 00000000 multi - uart17 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 00116c h D /(rdr117/(tdr117))[r/w] b,h,w -- ------ -------- * 3 rdr017/(tdr017)[r/w] b,h,w ------- 0 00000000* 1 001170 h sacsr17[r/w] b,h,w 0 ---- 000 00000000 stmr17[r] b,h,w 00000000 00000000 001174 h stmcr17[r/w] b,h,w 00000000 00000000 D /(sc scr17/sfur17)[r/w] b,h,w -------- -------- * 3 * 4 001178 h D /(scstr317)/ (lamsr17) [r/w] b,h,w -------- * 3 D /(scstr217)/ (lamcr17) [r/w] b,h,w -------- * 3 D /(scstr117)/(sflr11 7) [r/w] b,h,w -------- * 3 D /(scstr017)/(sflr01 7) [r/w] b,h,w -------- * 3 00117c h D D /(scsfr217) [r/w] b,h,w -------- * 3 D /(scsfr117) [r /w] b,h,w -------- * 3 D /(scsfr017) [r/w] b,h,w -------- * 3 001180 h D/(tbyte317)/ (lamesr17) [r/w] b,h,w -------- * 3 D/(tbyte217)/ (lamert17) [r/w] b,h,w -------- * 3 D/(tbyte117)/ (lamier17) [r/w] b,h,w -------- * 3 tbyte017/(lamrid 17)/(lamtid17) [r/w] b,h,w 0 0000000 001184 h bgr17[r/w] h,w 00000000 00000000 D /(ismk17) [r/w] b,h,w -------- * 2 D /(isba17) [r/w] b,h,w -------- * 2 001188 h fcr117 [r/w] b,h,w --- 00100 fcr017 [r/w] b,h,w - 0000000 fbyte17[r/w] b,h,w 00000000 00000000 00118c h fticr17[r/w] b,h,w 000 00000 00000000 D D d a t a s h e e t 84 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001190 h scr18/(ibcr18) [r/w] b,h,w 0 -- 00000 smr18 [r/w] b,h,w 000 - 00 - 0 ssr18 [r/w] b,h,w 0 - 000011 escr18/(ibsr18) [r/w] b,h,w 00000000 multi - uart18 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 001194 h D /(r dr118/(tdr118))[r/w] b,h,w -------- -------- * 3 rdr018/(tdr018)[ r/w] b,h,w ------- 0 00000000* 1 001198 h sacsr18[r/w] b,h,w 0 ---- 000 00000000 stmr18[r] b,h,w 00000000 00000000 00119c h stmcr18[r/w] b,h,w 00000000 00000000 D /(scs cr18/sfur18)[r/w] b,h,w -------- -------- * 3 * 4 0011a0 h D /(scstr318)/ (lamsr18) [r/w] b, h,w -------- * 3 D /(scstr218)/ (lamcr18) [r/w] b,h,w -------- * 3 D /(scstr118)/(sflr11 8) [r/w] b,h,w -------- * 3 D /(scstr018)/(sflr01 8) [r/w] b,h,w -------- * 3 0011a4 h D D /(scsfr218) [r/w] b,h,w -------- * 3 D /(scsfr118) [r/w] b,h,w -------- * 3 D /(scsfr018) [r/w] b,h,w -------- * 3 0011a8 h D/(tbyte318)/ (lamesr18) [r/w] b,h,w -------- * 3 D/(tbyte218)/ (lamert18) [r/w] b,h,w -------- * 3 D/(tbyte118)/ (lamier18) [r/w] b,h,w -------- * 3 tbyte018/(lamrid 18)/(lamtid18) [r/w] b,h,w 00000000 0011ac h bgr18[r/w] h,w 0 0000000 00000000 D /(ismk18) [r/w] b,h,w -------- * 2 D /(isba18) [r/w] b,h,w -------- * 2 0011b0 h fcr118 [r/w] b,h,w --- 00100 fcr018 [r/w] b,h,w - 0000000 fbyte18[r/w] b,h,w 00000000 00000000 0011b4 h fticr18[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 85 confidential address address offset value / register name block +0 +1 +2 +3 0011b8 h scr19 /(ibcr19) [r/w] b,h,w 0 -- 00000 smr19 [r/w] b,h,w 000 - 00 - 0 ssr19 [r/w] b,h,w 0 - 000011 escr19/(ibsr19) [r/w] b,h,w 00000000 multi - uart19 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 0011bc h D /( rdr119/(tdr119))[r/w] b,h,w -------- -------- * 3 rdr019/(tdr019)[r/w] b,h,w ------- 0 00000000* 1 0011c0 h sacsr19[r/w] b,h,w 0 ---- 000 00000000 stmr19[r] b,h,w 00000000 00000000 0011c4 h stmcr19[r/w] b,h,w 00000000 00000000 D /(sc scr19/sfur19)[r/w] b,h, w -------- -------- * 3 * 4 0011c8 h D /(scstr319)/ (lamsr19) [r/w] b,h,w -------- * 3 D /(scstr219)/ (lamcr19) [r/w] b,h,w -------- * 3 D /(scstr119)/(sflr11 9) [r/w] b,h,w -------- * 3 D /(scstr019)/(sflr01 9) [r/w] b,h,w -------- * 3 0011cc h D D /(scsfr219) [r/w] b,h,w -------- * 3 D /(scsfr119) [r/w] b,h,w -------- * 3 D /(scsfr019) [r/w] b,h,w -------- * 3 0011d0 h D/(tbyte319)/ (lamesr19) [r/w] b,h,w -------- * 3 D/(tbyte219)/ (lamert19) [r/w] b,h,w -------- * 3 D/(tbyte119)/ (lamier19) [r/w] b,h,w -------- * 3 tbyte019/( lamrid 19)/(lamtid19) [r/w] b,h,w 00000000 0011d4 h bgr19[r/w] h,w 00000000 00000000 D /(ismk19) [r/w] b,h,w -------- * 2 D /(isba19) [r/w] b,h,w -------- * 2 0011d8 h fcr119 [r/w] b,h,w --- 00100 fcr019 [r/w] b,h,w - 0000000 fbyte19[r/w] b,h,w 00000000 0000000 0 0011dc h fticr19[r/w] b,h,w 00000000 00000000 D D 0011e0 h to 0011fc h D D D D reserved 001200 h tcgs [r/w] b,h,w ------ 00 D D tcgse [r/w] b,h,w ----- 000 16 - bit free - run timer synchronous activation 001204 h cpclrb0/cpclr0 [w] h,w 11111111 11111111 tcdt 0 [r/w] h,w 00000000 00000000 16 - bit free - run timer 0 001208 h tccs0 [r/w] b,h,w 00000000 01000000 ---- 0000 -------- 00120c h cpclrb1/cpclr1 [w] h,w 11111111 11111111 tcdt1 [r/w] h,w 00000000 00000000 16 - bit free - run timer 1 001210 h tccs1 [r/w] b,h,w 000 00000 01000000 ---- 0000 -------- 001214 h cpclrb2/cpclr2 [w] h,w 11111111 11111111 tcdt2 [r/w] h,w 00000000 00000000 16 - bit free - run timer 2 001218 h tccs2 [r/w] b,h,w 00000000 01000000 ---- 0000 -------- 00121c h to 001230 h D D D D reserved d a t a s h e e t 86 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001234 h frs0 [r/w] b,h,w -------- -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 16 - bit free - run timer selection 001238 h D frs1 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 00123c h frs2 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 001240 h frs3 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 001244 h frs4 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 001248 h D D D D reserved 00124c h occpb0/occp0 [r/w] h,w 00000000 00000000 occpb1/occp1 [r/w] h,w 00000000 00000000 16 - bit output compare 0/1 001250 h ocs01 [r/w] b ,h,w - 110 -- 00 00001100 D ocmod01 [r/w] b,h,w ------ 00 001254 h occpb2/occp2 [r/w] h,w 00000000 00000000 occpb3/occp3 [r/w] h,w 00000000 00000000 16 - bit output compare 2/3 001258 h ocs23 [r/w] b,h,w - 110 -- 00 00001100 D ocmod23 [r/w] b,h,w ------ 00 0012 5c h occpb4/occp4 [r/w] h,w 00000000 00000000 occpb5/occp5 [r/w] h,w 00000000 00000000 16 - bit output compare 4/5 001260 h ocs45 [r/w] b,h,w - 110 -- 00 00001100 D ocmod45 [r/w] b,h,w ------ 00 001264 h to 001278 h D D D D reserved 00127c h ipcp0 [r] h,w 00000 000 00000000 ipcp1 [r] h,w 00000000 00000000 16 - bit input capture 0/1 001280 h ics01 [r/w] b,h,w ------ 00 00000000 D lsyns [r/w] b,h,w ---- 0000 001284 h ipcp2 [r] h,w 00000000 00000000 ipcp3 [r] h,w 00000000 00000000 16 - bit input capture 2/3 001288 h ics2 3 [r/w] b,h,w ------ 00 00000000 D D 00128c h to 001298 h D D D D reserved 00129c h D D D D reserved d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 87 confidential address address offset value / register name block +0 +1 +2 +3 0012a0 h tmrr0 [r/w] h,w 00000000 00000001 tmrr1 [r/w] h,w 00000000 00000001 waveform generator 0/1/2 0012a4 h tmrr2 [r/w] h,w 00000000 00000001 D D 0012a 8 h dtscr0 [r/w] b,h,w 00000000 dtscr1 [r/w] b,h,w 00000000 dtscr2 [r/w] b,h,w 00000000 D 0012ac h D dtir0 [r/w] b,h,w 000000 -- D dtmns0 [r/w] b,h,w 00 --- 000 0012b0 h D sigcr10 [r/w] b,h,w 00000000 D sigcr20 [r/w] b,h,w 000000 - 1 0012b4 h pics0 [r/w] b, h,w 000000 -- -------- -------- -------- 0012b8 h to 0012cc h D D D D reserved 0012d0 h frs5 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 16 - bit free - run timer selection a/d activation compare 0012d4 h frs6 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 0012d8 h frs7 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 0012dc h frs10 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 0012e0 h frs11 [r/w] b,h,w -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 0012e4 h to 0012fc h D D D D reserved 001300 h D reserved d a t a s h e e t 88 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 00130 4 h adtss0[r/w] b,h,w ------- 0 D D D 12 - bit a/d converter 1/2 unit 001308 h adtse0[r/w] b,h,w 00000000 00000000 00000000 00000000 00130c h adcomp0/adcompb0[r/w] h,w 00000000 00000000 adcomp1/adcompb1[r/w] h,w 00000000 00000000 001310 h adcomp2/adcompb2[r /w] h,w 00000000 00000000 adcomp3/adcompb3[r/w] h,w 00000000 00000000 001314 h adcomp4/adcompb4[r/w] h,w 00000000 00000000 adcomp5/adcompb5[r/w] h,w 00000000 00000000 001318 h adcomp6/adcompb6[r/w] h,w 00000000 00000000 adcomp7/adcompb7[r/w] h,w 00000000 00000000 00131c h adcomp8/adcompb8[r/w] h,w 00000000 00000000 adcomp9/adcompb9[r/w] h,w 00000000 00000000 001320 h adcomp10/adcompb10[r/w] h,w 00000000 00000000 adcomp11/adcompb11[r/w] h,w 00000000 00000000 001324 h adcomp12/adcompb12[r/w] h,w 00000000 00000000 adcomp13/adcompb13[r/w] h,w 00000000 00000000 001328 h adcomp14/adcompb14[r/w] h,w 00000000 00000000 adcomp15/adcompb15[r/w] h,w 00000000 00000000 00132c h adcomp16/adcompb16[r/w] h,w 00000000 00000000 adcomp17/adcompb17[r/w] h,w 00000000 00000 000 001330 h adcomp18/adcompb18[r/w] h,w 00000000 00000000 adcomp19/adcompb19[r/w] h,w 00000000 00000000 001334 h adcomp20/adcompb20[r/w] h,w 00000000 00000000 adcomp21/adcompb21[r/w] h,w 00000000 00000000 001338 h adcomp22/adcompb22[r/w] h,w 00000000 0 0000000 adcomp23/adcompb23[r/w] h,w 00000000 00000000 00133c h adcomp24/adcompb24[r/w] h,w 00000000 00000000 adcomp25/adcompb25[r/w] h,w 00000000 00000000 001340 h adcomp26/adcompb26[r/w] h,w 00000000 00000000 adcomp27/adcompb27[r/w] h,w 00000000 0000000 0 001344 h adcomp28/adcompb28[r/w] h,w 00000000 00000000 adcomp29/adcompb29[r/w] h,w 00000000 00000000 001348 h adcomp30/adcompb30[r/w] h,w 00000000 00000000 adcomp31/adcompb31[r/w] h,w 00000000 00000000 00134c h adtcs0[r/w] b,h,w 00000000 0010 ---- adtc s1[r/w] b,h,w 00000000 0010 ---- 001350 h adtcs2[r/w] b,h,w 00000000 0010 ---- adtcs3[r/w] b,h,w 00000000 0010 ---- 001354 h adtcs4[r/w] b,h,w 00000000 0010 ---- adtcs5[r/w] b,h,w 00000000 0010 ---- 001358 h adtcs6[r/w] b,h,w 00000000 0010 ---- adtcs7[r/w] b, h,w 00000000 0010 ---- 00135c h adtcs8[r/w] b,h,w 00000000 0010 ---- adtcs9[r/w] b,h,w 00000000 0010 ---- 001360 h adtcs10[r/w] b,h,w 00000000 0010 ---- adtcs11[r/w] b,h,w 00000000 0010 ---- 001364 h adtcs12[r/w] b,h,w 00000000 0010 ---- adtcs13[r/w] b,h,w 00 000000 0010 ---- 001368 h adtcs14[r/w] b,h,w 00000000 0010 ---- adtcs15[r/w] b,h,w 00000000 0010 ---- d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 89 confidential address address offset value / register name block +0 +1 +2 +3 00136c h adtcs16[r/w] b,h,w 00000000 0010 ---- adtcs17[r/w] b,h,w 00000000 0010 ---- 12 - bit a/d converter 1/2 unit 001370 h adtcs18[r/w] b,h,w 00000000 0010 - --- adtcs19[r/w] b,h,w 00000000 0010 ---- 001374 h adtcs20[r/w] b,h,w 00000000 0010 ---- adtcs21[r/w] b,h,w 00000000 0010 ---- 001378 h adtcs22[r/w] b,h,w 00000000 0010 ---- adtcs23[r/w] b,h,w 00000000 0010 ---- 00137c h adtcs24[r/w] b,h,w 00000000 0010 ---- adtcs25[r/w] b,h,w 00000000 0010 ---- 001380 h adtcs26[r/w] b,h,w 00000000 0010 ---- adtcs27[r/w] b,h,w 00000000 0010 ---- 001384 h adtcs28[r/w] b,h,w 00000000 0010 ---- adtcs29[r/w] b,h,w 00000000 0010 ---- 001388 h adtcs30[r/w] b,h,w 00000000 0010 ---- adtc s31[r/w] b,h,w 00000000 0010 ---- 00138c h adtcd0[r] b,h,w 10 -- 0000 00000000 adtcd1[r] b,h,w 10 -- 0000 00000000 001390 h adtcd2[r] b,h,w 10 -- 0000 00000000 adtcd3[r] b,h,w 10 -- 0000 00000000 001394 h adtcd4[r] b,h,w 10 -- 0000 00000000 adtcd5[r] b,h,w 10 -- 000 0 00000000 001398 h adtcd6[r] b,h,w 10 -- 0000 00000000 adtcd7[r] b,h,w 10 -- 0000 00000000 00139c h adtcd8[r] b,h,w 10 -- 0000 00000000 adtcd9[r] b,h,w 10 -- 0000 00000000 0013a0 h adtcd10[r] b,h,w 10 -- 0000 00000000 adtcd11[r] b,h,w 10 -- 0000 00000000 0013a4 h adtcd12[r] b,h,w 10 -- 0000 00000000 adtcd13[r] b,h,w 10 -- 0000 00000000 0013a8 h adtcd14[r] b,h,w 10 -- 0000 00000000 adtcd15[r] b,h,w 10 -- 0000 00000000 0013ac h adtcd16[r] b,h,w 10 -- 0000 00000000 adtcd17[r] b,h,w 10 -- 0000 00000000 0013b0 h adtcd18[r] b,h, w 10 -- 0000 00000000 adtcd19[r] b,h,w 10 -- 0000 00000000 0013b4 h adtcd20[r] b,h,w 10 -- 0000 00000000 adtcd21[r] b,h,w 10 -- 0000 00000000 0013b8 h adtcd22[r] b,h,w 10 -- 0000 00000000 adtcd23[r] b,h,w 10 -- 0000 00000000 0013bc h adtcd24[r] b,h,w 10 -- 0000 00000 000 adtcd25[r] b,h,w 10 -- 0000 00000000 0013c0 h adtcd26[r] b,h,w 10 -- 0000 00000000 adtcd27[r] b,h,w 10 -- 0000 00000000 0013c4 h adtcd28[r] b,h,w 10 -- 0000 00000000 adtcd29[r] b,h,w 10 -- 0000 00000000 0013c8 h adtcd30[r] b,h,w 10 -- 0000 00000000 adtcd31[r] b ,h,w 10 -- 0000 00000000 d a t a s h e e t 90 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0013cc h adtecs0[r/w] b,h,w ------- 0 --- 00000 adtecs1[r/w] b,h,w ------- 0 --- 00000 12 - bit a/d converter 1/2 unit 0013d0 h adtecs2[r/w] b,h,w ------- 0 --- 00000 adtecs3[r/w] b,h,w ------- 0 --- 00000 0013d4 h adtecs4[r/w] b,h,w ------- 0 --- 00000 adtecs5[r/w] b,h,w ------- 0 --- 00000 0013d8 h adtecs6[r/w] b,h,w ------- 0 --- 00000 adtecs7[r/w] b,h,w ------- 0 --- 00000 0013dc h adtecs8[r/w] b,h,w ------- 0 --- 00000 adtecs9[r/w] b,h,w ------- 0 --- 00000 0013e0 h adtecs10[r/w] b,h,w ------- 0 - -- 00000 adtecs11[r/w] b,h,w ------- 0 --- 00000 0013e4 h adtecs12[r/w] b,h,w ------- 0 --- 00000 adtecs13[r/w] b,h,w ------- 0 --- 00000 0013e8 h adtecs14[r/w] b,h,w ------- 0 --- 00000 adtecs15[r/w] b,h,w ------- 0 --- 00000 0013ec h adtecs16[r/w] b,h,w ------- 0 --- 00000 adtecs17[r/w] b,h,w ------- 0 --- 00000 0013f0 h adtecs18[r/w] b,h,w ------- 0 --- 00000 adtecs19[r/w] b,h,w ------- 0 --- 00000 0013f4 h adtecs20[r/w] b,h,w ------- 0 --- 00000 adtecs21[r/w] b,h,w ------- 0 --- 00000 0013f8 h adtecs22[r/w] b,h,w ------ - 0 --- 00000 adtecs23[r/w] b,h,w ------- 0 --- 00000 0013fc h adtecs24[r/w] b,h,w ------- 0 --- 00000 adtecs25[r/w] b,h,w ------- 0 --- 00000 001400 h adtecs26[r/w] b,h,w ------- 0 --- 00000 adtecs27[r/w] b,h,w ------- 0 --- 00000 001404 h adtecs28[r/w] b,h,w ---- --- 0 --- 00000 adtecs29[r/w] b,h,w ------- 0 --- 00000 001408 h adtecs30[r/w] b,h,w ------- 0 --- 00000 adtecs31[r/w] b,h,w ------- 0 --- 00000 00140c h adrcut0[r/w] b,h,w ---- 0000 00000000 adrclt0[r/w] b,h,w ---- 0000 00000000 001410 h adrcut1[r/w] b,h,w ---- 0 000 00000000 adrclt1[r/w] b,h,w ---- 0000 00000000 001414 h adrcut2[r/w] b,h,w ---- 0000 00000000 adrclt2[r/w] b,h,w ---- 0000 00000000 001418 h adrcut3[r/w] b,h,w ---- 0000 00000000 adrclt3[r/w] b,h,w ---- 0000 00000000 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 91 confidential address address offset value / register name block +0 +1 +2 +3 00141c h adrccs0[r/w] b,h,w 00000000 adrccs1[r/w] b,h,w 00000000 adrccs2[r/w] b,h,w 00000000 adrccs3[r/w] b,h,w 00000000 12 - bit a/d converter 1/2 unit 001420 h adrccs4[r/w] b,h,w 00000000 adrccs5[r/w] b,h,w 00000000 adrccs6[r/w] b,h,w 00000000 adrccs7[r/w] b,h,w 00000000 001424 h adr ccs8[r/w] b,h,w 00000000 adrccs9[r/w] b,h,w 00000000 adrccs10[r/w] b,h,w 00000000 adrccs11[r/w] b,h,w 00000000 001428 h adrccs12[r/w] b,h,w 00000000 adrccs13[r/w] b,h,w 00000000 adrccs14[r/w] b,h,w 00000000 adrccs15[r/w] b,h,w 00000000 00142c h a drccs16[r/w] b,h,w 00000000 adrccs17[r/w] b,h,w 00000000 adrccs18[r/w] b,h,w 00000000 adrccs19[r/w] b,h,w 00000000 001430 h adrccs20[r/w] b,h,w 00000000 adrccs21[r/w] b,h,w 00000000 adrccs22[r/w] b,h,w 00000000 adrccs23[r/w] b,h,w 00000000 00143 4 h adrccs24[r/w] b,h,w 00000000 adrccs25[r/w] b,h,w 00000000 adrccs26[r/w] b,h,w 00000000 adrccs27[r/w] b,h,w 00000000 001438 h adrccs28[r/w] b,h,w 00000000 adrccs29[r/w] b,h,w 00000000 adrccs30[r/w] b,h,w 00000000 adrccs31[r/w] b,h,w 00000000 0 0143c h adrcot0[r] b,h,w 00000000 00000000 00000000 00000000 001440 h adrcif0[r,w] b,h,w 00000000 00000000 00000000 00000000 001444 h adscans0[r/w] b,h,w 000 ----- D D D 001448 h adncs0[r/w] b,h,w 0 - 000 - 00 adncs1[r/w] b,h,w 0 - 000 - 00 adncs2[r/w] b,h,w 0 - 000 - 00 adncs3[r/w] b,h,w 0 - 000 - 00 00144c h adncs4[r/w] b,h,w 0 - 000 - 00 adncs5[r/w] b,h,w 0 - 000 - 00 adncs6[r/w] b,h,w 0 - 000 - 00 adncs7[r/w] b,h,w 0 - 000 - 00 001450 h adnc s8[r/w] b,h,w 0 - 000 - 00 adncs9[r/w] b,h,w 0 - 000 - 00 adncs10[r/w] b,h,w 0 - 000 - 00 adncs11[r/w] b,h,w 0 - 000 - 00 001454 h adncs12[r/w] b,h,w 0 - 000 - 00 adncs13[r/w] b,h,w 0 - 000 - 00 adncs14[r/w] b,h,w 0 - 000 - 00 adncs15[r/w] b,h,w 0 - 000 - 00 001458 h adprtf0[r] b,h,w 0 0000000 00000000 00000000 00000000 00145c h adeocf0[r] b,h,w 11111111 11111111 11111111 11111111 001460 h adcs0[r] b,h,w 0 ------- -------- adch0[r] b,h,w --- 00000 admd0[r/w] b,h,w 0 --- 0000 001464 h adstpcs0[r/w] b,h,w 00000000 adstpcs1[r/w] b,h,w 0000 0000 adstpcs2[r/w] b,h,w 00000000 adstpcs3[r/w] b,h,w 00000000 001468 h adstpcs4[r/w] b,h,w 00000000 adstpcs5[r/w] b,h,w 00000000 adstpcs6[r/w] b,h,w 00000000 adstpcs7[r/w] b,h,w 00000000 00146c h D d a t a s h e e t 92 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001470 h adtss1[r/w] b,h,w ------- 0 D D D 12 - bit a/d converter 2/2 unit 001474 h adtse1[r/w] b,h,w 00000000 00000000 00000000 00000000 001478 h adcomp32/adcompb32[r/w] h,w 00000000 00000000 adcomp33/adcompb33[r/w] h,w 00000000 00000000 00147c h adcomp34/adcompb34[r/w] h,w 00000000 00000000 adcomp35/ad compb35[r/w] h,w 00000000 00000000 001480 h adcomp36/adcompb36[r/w] h,w 00000000 00000000 adcomp37/adcompb37[r/w] h,w 00000000 00000000 001484 h adcomp38/adcompb38[r/w] h,w 00000000 00000000 adcomp39/adcompb39[r/w] h,w 00000000 00000000 001488 h adcomp4 0/adcompb40[r/w] h,w 00000000 00000000 adcomp41/adcompb41[r/w] h,w 00000000 00000000 00148c h adcomp42/adcompb42[r/w] h,w 00000000 00000000 adcomp43/adcompb43[r/w] h,w 00000000 00000000 001490 h adcomp44/adcompb44[r/w] h,w 00000000 00000000 adcomp45/adco mpb45[r/w] h,w 00000000 00000000 001494 h adcomp46/adcompb46[r/w] h,w 00000000 00000000 adcomp47/adcompb47[r/w] h,w 00000000 00000000 001498 h adcomp48/adcompb48[r/w] h,w 00000000 00000000 adcomp49/adcompb49[r/w] h,w 00000000 00000000 00149c h adcomp50 /adcompb50[r/w] h,w 00000000 00000000 adcomp51/adcompb51[r/w] h,w 00000000 00000000 0014a0 h adcomp52/adcompb52[r/w] h,w 00000000 00000000 adcomp53/adcompb53[r/w] h,w 00000000 00000000 0014a4 h adcomp54/adcompb54[r/w] h,w 00000000 00000000 adcomp55/adcom pb55[r/w] h,w 00000000 00000000 0014a8 h adcomp56/adcompb56[r/w] h,w 00000000 00000000 adcomp57/adcompb57[r/w] h,w 00000000 00000000 0014ac h adcomp58/adcompb58[r/w] h,w 00000000 00000000 adcomp59/adcompb59[r/w] h,w 00000000 00000000 0014b0 h adcomp60/a dcompb60[r/w] h,w 00000000 00000000 adcomp61/adcompb61[r/w] h,w 00000000 00000000 0014b4 h adcomp62/adcompb62[r/w] h,w 00000000 00000000 adcomp63/adcompb63[r/w] h,w 00000000 00000000 0014b8 h adtcs32[r/w] b,h,w 00000000 0010 ---- adtcs33[r/w] b,h,w 000000 00 0010 ---- 0014bc h adtcs34[r/w] b,h,w 00000000 0010 ---- adtcs35[r/w] b,h,w 00000000 0010 ---- 0014c0 h adtcs36[r/w] b,h,w 00000000 0010 ---- adtcs37[r/w] b,h,w 00000000 0010 ---- 0014c4 h adtcs38[r/w] b,h,w 00000000 0010 ---- adtcs39[r/w] b,h,w 00000000 0 010 ---- 0014c8 h adtcs40[r/w] b,h,w 00000000 0010 ---- adtcs41[r/w] b,h,w 00000000 0010 ---- 0014cc h adtcs42[r/w] b,h,w 00000000 0010 ---- adtcs43[r/w] b,h,w 00000000 0010 ---- 0014d0 h adtcs44[r/w] b,h,w 00000000 0010 ---- adtcs45[r/w] b,h,w 00000000 0010 - --- 0014d4 h adtcs46[r/w] b,h,w 00000000 0010 ---- adtcs47[r/w] b,h,w 00000000 0010 ---- d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 93 confidential address address offset value / register name block +0 +1 +2 +3 0014d8 h adtcs48[r/w] b,h,w 00000000 0010 ---- adtcs49[r/w] b,h,w 00000000 0010 ---- 12 - bit a/d converter 2/2 unit 0014dc h adtcs50[r/w] b,h,w 00000000 0010 ---- adtcs51 [r/w] b,h,w 00000000 0010 ---- 0014e0 h adtcs52[r/w] b,h,w 00000000 0010 ---- adtcs53[r/w] b,h,w 00000000 0010 ---- 0014e4 h adtcs54[r/w] b,h,w 00000000 0010 ---- adtcs55[r/w] b,h,w 00000000 0010 ---- 0014e8 h adtcs56[r/w] b,h,w 00000000 0010 ---- adtcs57[r/w ] b,h,w 00000000 0010 ---- 0014ec h adtcs58[r/w] b,h,w 00000000 0010 ---- adtcs59[r/w] b,h,w 00000000 0010 ---- 0014f0 h adtcs60[r/w] b,h,w 00000000 0010 ---- adtcs61[r/w] b,h,w 00000000 0010 ---- 0014f4 h adtcs62[r/w] b,h,w 00000000 0010 ---- adtcs63[r/w] b, h,w 00000000 0010 ---- 0014f8 h adtcd32[r] b,h,w 10 -- 0000 00000000 adtcd33[r] b,h,w 10 -- 0000 00000000 0014fc h adtcd34[r] b,h,w 10 -- 0000 00000000 adtcd35[r] b,h,w 10 -- 0000 00000000 001500 h adtcd36[r] b,h,w 10 -- 0000 00000000 adtcd37[r] b,h,w 10 -- 0000 000 00000 001504 h adtcd38[r] b,h,w 10 -- 0000 00000000 adtcd39[r] b,h,w 10 -- 0000 00000000 001508 h adtcd40[r] b,h,w 10 -- 0000 00000000 adtcd41[r] b,h,w 10 -- 0000 00000000 00150c h adtcd42[r] b,h,w 10 -- 0000 00000000 adtcd43[r] b,h,w 10 -- 0000 00000000 001510 h adtcd44[r] b,h,w 10 -- 0000 00000000 adtcd45[r] b,h,w 10 -- 0000 00000000 001514 h adtcd46[r] b,h,w 10 -- 0000 00000000 adtcd47[r] b,h,w 10 -- 0000 00000000 001518 h adtcd48[r] b,h,w 10 -- 0000 00000000 adtcd49[r] b,h,w 10 -- 0000 00000000 00151c h adtcd50[r] b,h,w 10 -- 0000 00000000 adtcd51[r] b,h,w 10 -- 0000 00000000 001520 h adtcd52[r] b,h,w 10 -- 0000 00000000 adtcd53[r] b,h,w 10 -- 0000 00000000 001524 h adtcd54[r] b,h,w 10 -- 0000 00000000 adtcd55[r] b,h,w 10 -- 0000 00000000 001528 h adtcd56[r] b,h,w 10 -- 0000 000000 00 adtcd57[r] b,h,w 10 -- 0000 00000000 00152c h adtcd58[r] b,h,w 10 -- 0000 00000000 adtcd59[r] b,h,w 10 -- 0000 00000000 001530 h adtcd60[r] b,h,w 10 -- 0000 00000000 adtcd61[r] b,h,w 10 -- 0000 00000000 001534 h adtcd62[r] b,h,w 10 -- 0000 00000000 adtcd63[r] b, h,w 10 -- 0000 00000000 d a t a s h e e t 94 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001538 h adtecs32[r/w] b,h,w ------- 0 --- 00000 adtecs33[r/w] b,h,w ------- 0 --- 00000 12 - bit a/d converter 2/2 unit 00153c h adtecs34[r/w] b,h,w ------- 0 --- 00000 adtecs35[r/w] b,h,w ------- 0 --- 00000 001540 h adtecs36[r/w] b,h,w --- ---- 0 --- 00000 adtecs37[r/w] b,h,w ------- 0 --- 00000 001544 h adtecs38[r/w] b,h,w ------- 0 --- 00000 adtecs39[r/w] b,h,w ------- 0 --- 00000 001548 h adtecs40[r/w] b,h,w ------- 0 --- 00000 adtecs41[r/w] b,h,w ------- 0 --- 00000 00154c h adtecs42[r/w] b,h,w - ------ 0 --- 00000 adtecs43[r/w] b,h,w ------- 0 --- 00000 001550 h adtecs44[r/w] b,h,w ------- 0 --- 00000 adtecs45[r/w] b,h,w ------- 0 --- 00000 001554 h adtecs46[r/w] b,h,w ------- 0 --- 00000 adtecs47[r/w] b,h,w ------- 0 --- 00000 001558 h adtecs48[r/w] b,h, w ------- 0 --- 00000 adtecs49[r/w] b,h,w ------- 0 --- 00000 00155c h adtecs50[r/w] b,h,w ------- 0 --- 00000 adtecs51[r/w] b,h,w ------- 0 --- 00000 001560 h adtecs52[r/w] b,h,w ------- 0 --- 00000 adtecs53[r/w] b,h,w ------- 0 --- 00000 001564 h adtecs54[r/w] b, h,w ------- 0 --- 00000 adtecs55[r/w] b,h,w ------- 0 --- 00000 001568 h adtecs56[r/w] b,h,w ------- 0 --- 00000 adtecs57[r/w] b,h,w ------- 0 --- 00000 00156c h adtecs58[r/w] b,h,w ------- 0 --- 00000 adtecs59[r/w] b,h,w ------- 0 --- 00000 001570 h adtecs60[r/w] b,h,w ------- 0 --- 00000 adtecs61[r/w] b,h,w ------- 0 --- 00000 001574 h adtecs62[r/w] b,h,w ------- 0 --- 00000 adtecs63[r/w] b,h,w ------- 0 --- 00000 001578 h adrcut4[r/w] b,h,w ---- 0000 00000000 adrclt4[r/w] b,h,w ---- 0000 00000000 00157c h adrcut5[r/w] b ,h,w ---- 0000 00000000 adrclt5[r/w] b,h,w ---- 0000 00000000 001580 h adrcut6[r/w] b,h,w ---- 0000 00000000 adrclt6[r/w] b,h,w ---- 0000 00000000 001584 h adrcut7[r/w] b,h,w ---- 0000 00000000 adrclt7[r/w] b,h,w ---- 0000 00000000 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 95 confidential address address offset value / register name block +0 +1 +2 +3 001588 h adrccs32[r/w] b,h ,w 00000000 adrccs33[r/w] b,h,w 00000000 adrccs34[r/w] b,h,w 00000000 adrccs35[r/w] b,h,w 00000000 12 - bit a/d converter 2/2 unit 00158c h adrccs36[r/w] b,h,w 00000000 adrccs37[r/w] b,h,w 00000000 adrccs38[r/w] b,h,w 00000000 adrccs39[r/w] b,h,w 0000 0000 001590 h adrccs40[r/w] b,h,w 00000000 adrccs41[r/w] b,h,w 00000000 adrccs42[r/w] b,h,w 00000000 adrccs43[r/w] b,h,w 00000000 001594 h adrccs44[r/w] b,h,w 00000000 adrccs45[r/w] b,h,w 00000000 adrccs46[r/w] b,h,w 00000000 adrccs47[r/w] b,h,w 00000000 001598 h adrccs48[r/w] b,h,w 00000000 adrccs49[r/w] b,h,w 00000000 adrccs50[r/w] b,h,w 00000000 adrccs51[r/w] b,h,w 00000000 00159c h adrccs52[r/w] b,h,w 00000000 adrccs53[r/w] b,h,w 00000000 adrccs54[r/w] b,h,w 00000000 adrccs55[r/w] b, h,w 00000000 0015a0 h adrccs56[r/w] b,h,w 00000000 adrccs57[r/w] b,h,w 00000000 adrccs58[r/w] b,h,w 00000000 adrccs59[r/w] b,h,w 00000000 0015a4 h adrccs60[r/w] b,h,w 00000000 adrccs61[r/w] b,h,w 00000000 adrccs62[r/w] b,h,w 00000000 adrccs63[r/w] b,h,w 00000000 0015a8 h adrcot1 [r] b,h,w 00000000 00000000 00000000 00000000 0015ac h adrcif1 [r,w] b,h,w 00000000 00000000 00000000 00000000 0015b0 h adscans1 [r/w] b,h,w 000 ----- D D D 0015b4 h adncs16 [r/w] b,h,w 0 - 000 - 00 adncs17 [r/w] b,h,w 0 - 0 00 - 00 adncs18 [r/w] b,h,w 0 - 000 - 00 adncs19 [r/w] b,h,w 0 - 000 - 00 0015b8 h adncs20 [r/w] b,h,w 0 - 000 - 00 adncs21 [r/w] b,h,w 0 - 000 - 00 adncs22 [r/w] b,h,w 0 - 000 - 00 adncs23 [r/w] b,h,w 0 - 000 - 00 0015bc h adncs24 [r/w] b,h,w 0 - 000 - 00 adncs25 [r/w] b,h,w 0 - 000 - 0 0 adncs26 [r/w] b,h,w 0 - 000 - 00 adncs27 [r/w] b,h,w 0 - 000 - 00 0015c0 h adncs28 [r/w] b,h,w 0 - 000 - 00 adncs29 [r/w] b,h,w 0 - 000 - 00 adncs30 [r/w] b,h,w 0 - 000 - 00 adncs31 [r/w] b,h,w 0 - 000 - 00 0015c4 h adprtf1 [r] b,h,w 00000000 00000000 00000000 00000000 0015 c8 h adeocf1 [r] b,h,w 11111111 11111111 11111111 11111111 0015cc h adcs1 [r] b,h,w 0 ------- -------- adch1 [r] b,h,w --- 00000 admd1 [r/w] b,h,w 0 --- 0000 0015d0 h adstpcs8 [r/w] b,h,w 00000000 adstpcs9 [r/w] b,h,w 00000000 adstpcs10 [r/w] b,h,w 00000000 adstpcs11 [r/w] b,h,w 00000000 0015d4 h adstpcs12[r/w] b,h,w 00000000 adstpcs13[r/w] b,h,w 00000000 adstpcs14[r/w] b,h,w 00000000 adstpcs15[r/w] b,h,w 00000000 d a t a s h e e t 96 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0015d8 h to 00174c h D D D D reserved 0 0 1750 h scr0/(ibcr0)[r/w] b,h,w 0 -- 00000 smr0[r/w] b,h,w 000 - 00 - 0 ssr0[r/w] b,h,w 0 - 000011 escr0/(ibsr0)[r/w] b,h,w 00000000 multi - uart0 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 001754 h D /(rdr10 /(tdr10))[r/w] b,h,w -------- -------- * 3 rdr00/(tdr00)[r/w] b,h,w ----- -- 0 00000000* 1 001758 h sacsr0[r/w] b,h,w 0 ---- 000 00000000 stmr0[r] b,h,w 00000000 00000000 00175c h stmcr0[r/w] b,h,w 00000000 00000000 D /(scscr0/sfur0)[r/w] b,h,w -------- -------- * 3 * 4 001760 h D /(scstr30)/ (lamsr0) [r/w] b,h,w -------- * 3 D /(scs tr20)/ (lamcr0) [r/w] b,h,w -------- * 3 D /(scstr10) /(sflr10) [r/w] b,h,w -------- * 3 D /(scstr00)/ (sflr00) [r/w] b,h,w -------- * 3 001764 h D D /(scsfr20) [r/w] b,h,w -------- * 3 D /(scsfr10) [r/w] b,h,w -------- * 3 D /(scsfr00) [r/w] b,h,w -------- * 3 001 768 h D/(tbyte30)/ (lamesr0) [r/w] b,h,w -------- * 3 D/(tbyte20) /(lamert0) [r/w] b,h,w -------- * 3 D/(tbyte10)/ (lamier0) [r/w] b,h,w -------- * 3 tbyte00/(lamrid0) /(lamtid0) [r/w] b,h,w 00000000 00176c h bgr0[r/w] h, w 00000000 00000000 D /(ismk0) [r/w] b,h ,w -------- * 2 D /(isba0) [r/w] b,h,w -------- * 2 001770 h fcr10[r/w] b,h,w --- 00100 fcr00[r/w] b,h,w - 0000000 fbyte0[r/w] b,h,w 00000000 00000000 001774 h fticr0[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 97 confidential address address offset value / register name block +0 +1 +2 +3 001778 h scr1/(ibcr1) [r/w] b,h,w 0 -- 00000 smr1[r/w] b,h, w 000 - 00 - 0 ssr1[r/w] b,h,w 0 - 000011 escr1/(ibsr1)[r/w] b,h,w 00000000 multi - uart1 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set imm ediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 00177c h D /(rdr11/(tdr11))[r/w] b,h,w -------- -------- * 3 rdr01/(tdr01)[r/w] b,h,w ------- 0 00000000* 1 001780 h sacsr1[r/w] b,h,w 0 ---- 000 00000000 stmr1[r] b,h,w 00000000 00000000 001784 h stmcr1[r/w] b,h,w 00000000 00000000 D /(scscr1/sfur1)[r/w] b,h,w ------- - -------- * 3 * 4 001788 h D /(scstr31)/ (lamsr1) [r/w] b,h,w -------- * 3 D /(scstr21)/ (lamcr1) [r/w] b,h,w -------- * 3 D /(scstr11)/ (sflr11) [r/w] b,h,w -------- * 3 D /(scstr01)/ (sflr01) [r/w] b,h,w -------- * 3 00178c h D D /(scsfr21)[r/w] b,h,w -------- * 3 D /(scsfr11) [r/w] b,h,w -------- * 3 D /(scsfr01) [r/w] b,h,w -------- * 3 001790 h D/(tbyte31)/ (lamesr1) [r/w] b,h,w -------- * 3 D/(tbyte21)/ (lamert1) [r/w] b,h,w -------- * 3 D/(tbyte11)/ (lamier1) [r/w] b,h,w -------- * 3 tbyte01/(lamrid1) /(lamtid1) [r/ w] b,h,w 00000000 001794 h bgr1[r/w] h,w 00000000 00000000 D /(ismk1)[r/w] b,h,w -------- * 2 D /(isba1)[r/w] b,h,w -------- * 2 001798 h fcr11[r/w] b,h,w --- 00100 fcr01[r/w] b,h,w - 0000000 fbyte1[r/w] b,h,w 00000000 00000000 00179c h fticr1[r/w] b,h,w 00 000000 00000000 D D d a t a s h e e t 98 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0017a0 h scr2/(ibcr2)[r/w] b,h,w 0 -- 00000 smr2[r/w] b,h,w 000 - 00 - 0 ssr2[r/w] b,h,w 0 - 000011 escr2/(ibsr2)[r/w] b,h,w 00000000 multi - uart2 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is no t set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 0017a4 h D /(rdr1 2/(tdr12))[r/w] b,h,w -------- -------- * 3 rdr02/(tdr02)[r/w] b,h,w --- ---- 0 00000000* 1 0017a8 h sacsr2[r/w] b,h,w 0 ---- 000 00000000 stmr2[r] b,h,w 00000000 00000000 0017ac h stmcr2[r/w] b,h,w 00000000 00000000 D /(scsc r2/sfur2)[r/w] b,h,w -------- -------- * 3 * 4 0017b0 h D /(scstr32)/ (lamsr2) [r/w] b,h,w -------- * 3 D /(s cstr22)/ (lamcr2) [r/w] b,h,w -------- * 3 D /(scstr12)/ (sflr12) [r/w] b,h,w -------- * 3 D /(scstr02)/ (sflr02) [r/w] b,h,w -------- * 3 0017b4 h D D /(scsfr22) [r/w] b,h,w -------- * 3 D /(scsfr12) [r/w] b,h,w -------- * 3 D /(scsfr02) [r/w] b,h,w -------- * 3 0017b8 h D/(tbyte32)/ (lamesr2) [r/w] b,h,w -------- * 3 D/(tbyte22)/ (lamert2) [r/w] b,h,w -------- * 3 D/(tbyte12)/ (lamier2) [r/w] b,h,w -------- * 3 tbyte02/(lamrid2) /(lamtid2) [r/w] b,h,w 00000000 0017bc h bgr2[r/w] h, w 00000000 00000000 D /(ismk2)[r/w] b,h,w -------- * 2 D /(isba2)[r/w] b,h,w -------- * 2 0017c0 h fcr12[r/w] b,h,w --- 00100 fcr02[r/w] b,h,w - 0000000 fbyte2[r/w] b,h,w 00000000 00000000 0017c4 h fticr2[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 99 confidential address address offset value / register name block +0 +1 +2 +3 0017c8 h scr3/(ibcr3) [r/w] b,h,w 0 -- 00000 smr3[r/w] b, h,w 000 - 00 - 0 ssr3[r/w] b,h,w 0 - 000011 escr3/(ibsr3)[r/w] b,h,w 00000000 multi - uart3 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set i mmediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 0017cc h D /(rdr13/ (tdr13))[r/w] b,h,w -------- -------- * 3 rdr03/(tdr03)[r/w] b,h,w ------- 0 00000000* 1 0017d0 h sacsr3[r/w] b,h,w 0 ---- 000 00000000 stmr3[r] b,h,w 00000000 00000000 0017d4 h stmcr3[r/w] b,h,w 00000000 00000000 D /(sc scr3/sfur3)[r/w] b,h,w ------- - -------- * 3 * 4 0017d8 h D /(scstr33)/ (lamsr3) [r/w] b,h,w -------- * 3 D /(scstr23)/ (lamcr3) [r/w] b,h,w -------- * 3 D /(scstr13)/ (sflr13) [r/w] b,h,w -------- * 3 D /(scstr03)/ (sflr03) [r/w] b,h,w -------- * 3 0017dc h D D /(scsfr23) [r/w] b,h,w ------- - * 3 D /(scsfr13) [r/w] b,h,w -------- * 3 D /(scsfr03) [r/w] b,h,w -------- * 3 0017e0 h D/(tbyte33)/ (lamesr3) [r/w] b,h,w -------- * 3 D/(tbyte23)/ (lamert3) [r/w] b,h,w -------- * 3 D/(tbyte13)/ (lamier3) [r/w] b,h,w -------- * 3 tbyte03/(lamrid3) /(lamtid3) [r /w] b,h,w 00000000 0017e4 h bgr3[r/w] h, w 00000000 00000000 D /(ismk3)[r/w] b,h,w -------- * 2 D /(isba3)[r/w] b,h,w -------- * 2 0017e8 h fcr13[r/w] b,h,w --- 00100 fcr03[r/w] b,h,w - 0000000 fbyte3[r/w] b,h,w 00000000 00000000 0017ec h fticr3[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 100 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0017f0 h scr4/(ibcr4) [r/w] b,h,w 0 -- 00000 smr4[r/w] b,h,w 000 - 00 - 0 ssr4[r/w] b,h,w 0 - 000011 escr4/(ibsr4)[r/w] b,h,w 00000000 multi - uart4 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 0017f4 h D /(rdr14/( tdr14))[r/w] b,h,w -------- -------- * 3 rdr04/(tdr04)[r/w] b,h,w ------- 0 00000000* 1 0017f8 h sacsr4[r/w] b,h,w 0 ---- 000 00000000 stmr4[r] b,h,w 00000000 00000000 0017fc h stmcr4[r/w] b,h,w 00000000 00000000 D /(sc scr4/sfur4)[r/w] b,h,w -------- -------- * 3 * 4 001800 h D /(scstr34)/ (lamsr4) [r/w] b,h,w -------- * 3 D /(scstr24)/ (lamcr4) [r/w] b,h,w -------- * 3 D /(scstr14)/ (sflr14) [r/w] b,h,w -------- * 3 D /(scstr04)/ (sflr04) [r/w] b,h,w -------- * 3 001804 h D D /(scsfr24) [r/w] b,h,w -------- * 3 D /(scsfr14) [r/w] b,h,w -------- * 3 D /(scsfr04) [r/w] b,h,w -------- * 3 001808 h D/(tbyte34)/ (lamesr4) [r/w] b,h,w -------- * 3 D/(tbyte24)/ (lamert4) [r/w] b,h,w -------- * 3 D/(tbyte14)/ (lamier4) [r/w] b,h,w -------- * 3 tbyte04/(lamrid4) /(lamtid4) [r/w] b,h,w 00000000 00180c h bgr4[r/w] h, w 00000000 00000000 D /(ismk4)[r/w ] b,h,w -------- * 2 D /(isba4)[r/w] b,h,w -------- * 2 001810 h fcr14[r/w] b,h,w --- 00100 fcr04[r/w] b,h,w - 0000000 fbyte4[r/w] b,h,w 00000000 00000000 001814 h fticr4[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 101 confidential address address offset value / register name block +0 +1 +2 +3 001818 h scr5/(ibcr5) [r/w] b,h,w 0 -- 00000 smr5[r/w] b,h,w 000 - 00 - 0 ssr5[r/w] b,h,w 0 - 000011 escr5/(ibsr5)[r/w] b,h,w 00000000 multi - uart5 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 00181c h D /(rdr15 /(tdr15))[r/w] b,h,w -------- -------- * 3 rdr05/(tdr05)[r/w] b,h,w ------- 0 00000000* 1 001820 h sacsr5[r/w] b,h,w 0 ---- 000 00000000 stmr5[r] b,h,w 00000000 00000000 001824 h stmcr5[r/w] b,h,w 00000000 00000000 D /(sc scr5/sfur5)[r/w] b,h,w ------- - -------- * 3 * 4 001828 h D /(scstr35)/ (lamsr5) [r/w] b,h,w -------- * 3 D /(scstr25)/ (lamcr5) [r/w] b,h,w -------- * 3 D /(scstr15)/ (sflr15) [r/w] b,h,w -------- * 3 D /(scstr05)/ (sflr05) [r/w] b,h,w -------- * 3 00182c h D D /(scsfr25) [r/w] b,h,w -------- * 3 D /(scsfr15) [r/w] b,h,w -------- * 3 D /(scsfr05) [r/w] b,h,w -------- * 3 001830 h D/(tbyte35)/ (lamesr5) [r/w] b,h,w -------- * 3 D/(tbyte25)/ (lamert5) [r/w] b,h,w -------- * 3 D/(tbyte15)/ (lamier5) [r/w] b,h,w -------- * 3 tbyte05/(lamrid5) /(lamtid5) [r /w] b,h,w 00000000 001834 h bgr5[r/w] h, w 00000000 00000000 D /(ismk5)[r/w] b,h,w -------- * 2 D /(isba5)[r/w] b,h,w -------- * 2 001838 h fcr15[r/w] b,h,w --- 00100 fcr05[r/w] b,h,w - 0000000 fbyte5[r/w] b,h,w 00000000 00000000 00183c h fticr5[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 102 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001840 h scr6/(ibcr6) [r/w] b,h,w 0 -- 00000 smr6[r/w] b,h,w 000 - 00 - 0 ssr6[r/w] b,h,w 0 - 000011 escr6/(ibsr6)[r/w] b,h,w 00000000 multi - uart6 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 001844 h D /(rd r16/(tdr16))[r/w] b,h,w -------- -------- * 3 rdr06/(tdr06)[r/w] b,h,w ------- 0 00000000* 1 001848 h sacsr6[r/w] b,h,w 0 ---- 000 00000000 stmr6[r] b,h,w 00000000 00000000 00184c h stmcr6[r/w] b,h,w 00000000 00000000 D /(s cscr6/sfur6)[r/w] b,h,w -------- -------- * 3 * 4 001850 h D /(scstr36)/ (lamsr6) [r/w] b,h,w -------- * 3 D /(scstr26)/ (lamcr6) [r/w] b,h,w -------- * 3 D /(scstr16)/ (sflr16) [r/w] b,h,w -------- * 3 D /(scstr06)/ (sflr06) [r/w] b,h,w -------- * 3 001854 h D D /(scsfr26) [r/w] b,h,w -------- * 3 D /(scsfr16) [r/w] b,h,w -------- * 3 D /(scsfr06) [r/w] b,h,w -------- * 3 001858 h D/(tbyte36)/ (lamesr6) [r/w] b,h,w -------- * 3 D/(tbyte26)/ (lamert6) [r/w] b,h,w -------- * 3 D/(tbyte16)/ (lamier6) [r/w] b,h,w -------- * 3 tbyte06/(lamrid6) /(lamtid6) [r/w] b,h,w 00000000 00185c h bgr6[r/w] h, w 00000000 00000000 D /(ismk6)[r/ w] b,h,w -------- * 2 D /(isba6)[r/w] b,h,w -------- * 2 001860 h fcr16[r/w] b,h,w --- 00100 fcr06[r/w] b,h,w - 0000000 fbyte6[r/w] b,h,w 00000000 00000000 001864 h fticr6[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 103 confidential address address offset value / register name block +0 +1 +2 +3 001868 h scr7/(ibcr7) [r/w] b,h,w 0 -- 00000 smr7[r/w] b,h,w 000 - 00 - 0 ssr7[r/w] b,h,w 0 - 000011 escr7/(ibsr7)[r/w] b,h,w 00000000 multi - uart7 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not se t immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 00186c h D / (rdr17/(tdr17))[r/w] b,h,w -------- -------- * 3 rdr07/(tdr07)[r/w] b,h,w ------- 0 00000000* 1 001870 h sacsr7[r/w] b,h,w 0 ---- 000 00000000 stmr7[r] b,h,w 00000000 00000000 001874 h stmcr7[r/w] b,h,w 00000000 00000000 D /(s cscr7/sfur7)[r/w] b,h,w ------- - -------- * 3 * 4 001878 h D /(scstr37)/ (lamsr7) [r/w] b,h,w -------- * 3 D /(scstr27)/ (lamcr7) [r/w] b,h,w -------- * 3 D /(scstr17)/ (sflr17) [r/w] b,h,w -------- * 3 D /(scstr07)/ (sflr07) [r/w] b,h,w -------- * 3 00187c h D D /(scsfr27) [r/w] b,h,w -------- * 3 D /(scsfr17) [r/w] b,h,w -------- * 3 D /(scsfr07) [r/w] b,h,w -------- * 3 001880 h D/(tbyte37)/ (lamesr7) [r/w] b,h,w -------- * 3 D/(tbyte27)/ (lamert7) [r/w] b,h,w -------- * 3 D/(tbyte17)/ (lamier7) [r/w] b,h,w -------- * 3 tbyte07/(lamrid7) /(lamtid7) [r /w] b,h,w 00000000 001884 h bgr7[r/w] h, w 00000000 00000000 D /(ismk7)[r/w] b,h,w -------- * 2 D /(isba7)[r/w] b,h,w -------- * 2 001888 h fcr17[r/w] b,h,w --- 00100 fcr07[r/w] b,h,w - 0000000 fbyte7[r/w] b,h,w 00000000 00000000 00188c h fticr7[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 104 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001890 h scr8/(ibcr8) [r/w] b,h,w 0 -- 00000 smr8[r/w] b,h,w 000 - 00 - 0 ssr8[r/w] b,h,w 0 - 000011 escr8/(ibsr8)[r/w] b,h,w 00000000 multi - uart8 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 001894 h D /( rdr18/(tdr18))[r/w] b,h,w -------- -------- * 3 rdr08/(tdr08)[r/w] b,h,w ------- 0 00000000* 1 001898 h sacsr8[r/w] b,h,w 0 ---- 000 00000000 stmr8[r] b,h,w 00000000 00000000 00189c h stmcr8[r/w] b,h,w 00000000 00000000 D /(sc scr8/sfur8)[r/w] b,h,w -------- -------- * 3 * 4 0018a0 h D /(scstr38)/ (lamsr8) [r/w] b,h,w -------- * 3 D /(scstr28)/ (lamcr8) [r/w] b,h,w -------- * 3 D /(scstr18)/ (sflr18) [r/w] b,h,w -------- * 3 D /(scstr08)/ (sflr08) [r/w] b,h,w -------- * 3 0018a4 h D D /(scsfr28) [r/w] b,h,w -------- * 3 D /(scsfr18) [r/w] b,h,w -------- * 3 D /(scsfr08) [r/w] b,h,w -------- * 3 0018a8 h D/(tbyte38)/ (lamesr8) [r/w] b,h,w -------- * 3 D/(tbyte28)/ (lamert8) [r/w] b,h,w -------- * 3 D/(tbyte18)/ (lamier8) [r/w] b,h,w -------- * 3 tbyte08/(lamrid8) /(lamtid8) [r/w] b,h,w 00000000 0018ac h bgr8[r/w] h,w 00000000 00000000 D /(ismk8)[r/w] b,h,w -------- * 2 D /(isba8)[r/w] b,h,w -------- * 2 0018b0 h fcr18[r/w] b,h,w --- 00100 fcr08[r/w] b,h,w - 0000000 fbyte8[r/w] b,h,w 00000000 00000000 0018b4 h fticr8[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 105 confidential address address offset value / register name block +0 +1 +2 +3 0018b8 h scr9/(ibcr9) [r/w] b,h,w 0 -- 00000 smr9[r/w] b ,h,w 000 - 00 - 0 ssr9[r/w] b,h,w 0 - 000011 escr9/(ibsr9)[r/w] b,h,w 00000000 multi - uart9 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 0018bc h D /(r dr19/(tdr19))[r/w] b,h,w -------- -------- * 3 rdr09/(tdr09)[r/w] b,h,w ------- 0 00000000* 1 0018c0 h sacsr9[r/w] b,h,w 0 ---- 000 00000000 stmr9[r] b,h,w 00000000 00000000 0018c4 h stmcr9[r/w] b,h,w 00000000 00000000 D /(s cscr9/sfur9)[r/w] b,h,w ------- - -------- * 3 * 4 0018c8 h D /(scstr39)/ (lamsr9) [r/w] b,h,w -------- * 3 D /(scstr29)/ (lamcr9) [r/w] b,h,w -------- * 3 D /(scstr19)/ (sflr19) [r/w] b,h,w -------- * 3 D /(scstr09)/ (sflr09) [r/w] b,h,w -------- * 3 0018cc h D D /(scsfr29) [r/w] b,h,w -------- * 3 D /(scsfr19) [r/w] b,h,w -------- * 3 D /(scsfr09) [r/w] b,h,w -------- * 3 0018d0 h D/(tbyte39)/ (lamesr9) [r/w] b,h,w -------- * 3 D/(tbyte29)/ (lamert9) [r/w] b,h,w -------- * 3 D/(tbyte19)/ (lamier9) [r/w] b,h,w -------- * 3 tbyte09/(lamrid9) /(lamtid9) [r/ w] b,h,w 00000000 0018d4 h bgr9[r/w] h, w 00000000 00000000 D /(ismk9)[r/w] b,h,w -------- * 2 D /(isba9)[r/w] b,h,w -------- * 2 0018d8 h fcr19[r/w] b,h,w --- 00100 fcr09[r/w] b,h,w - 0000000 fbyte9[r/w] b,h,w 00000000 00000000 0018dc h fticr9[r/w] b,h,w 0 0000000 00000000 D D d a t a s h e e t 106 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0018e0 h scr10/(ibcr10) [r/w] b,h,w 0 -- 00000 smr10[r/w] b,h,w 000 - 00 - 0 ssr10[r/w] b,h,w 0 - 000011 escr10/(ibsr10) [r/w] b,h,w 00000000 multi - uart10 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 0018e4 h D /( rdr110/(tdr110))[r/w] b,h,w -------- -------- * 3 rdr010/(tdr010)[ r/w] b,h,w ------- 0 00000000* 1 0018e8 h sacsr10[r/w] b,h,w 0 ---- 000 00000000 stmr10[r] b,h,w 00000000 00000000 0018ec h stmcr10[r/w] b,h,w 00000000 00000000 D / (scscr10/sfur10)[r/w] b,h,w -------- -------- * 3 * 4 0018f0 h D /(scstr310)/ (lamsr10) [r/w] b, h,w -------- * 3 D /(scstr210)/ (lamcr10) [r/w] b,h,w -------- * 3 D /(scstr110)/ (sflr110)[r/w] b,h,w -------- * 3 D /(scstr010)/ (sflr010)[r/w] b,h,w -------- * 3 0018f4 h D D /(scsfr210) [r/w] b,h,w -------- * 3 D /(scsfr110) [r/w] b,h,w -------- * 3 D /(scsfr01 0) [r/w] b,h,w -------- * 3 0018f8 h D/(tbyte310)/ (lamesr10) [r/w] b,h,w -------- * 3 D/(tbyte210)/ (lamert10) [r/w] b,h,w -------- * 3 D/(tbyte110)/ (lamier10) [r/w] b,h,w -------- * 3 tbyte010/(lamrid 10)/(lamtid10) [r/w] b,h,w 00000000 0018fc h bgr10[r/w] h, w 00000000 00000000 D /(ismk10)[r/w] b,h,w -------- * 2 D /(isba10)[r/w] b,h,w -------- * 2 001900 h fcr110[r/w] b,h,w --- 00100 fcr010[r/w] b,h,w - 0000000 fbyte10[r/w] b,h,w 00000000 00000000 001904 h fticr10[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 107 confidential address address offset value / register name block +0 +1 +2 +3 001908 h scr 11/(ibcr11) [r/w] b,h,w 0 -- 00000 smr11[r/w] b,h,w 000 - 00 - 0 ssr11[r/w] b,h,w 0 - 000011 escr11/(ibsr11) [r/w] b,h,w 00000000 multi - uart11 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 00190c h D /(rd r111/(tdr111))[r/w] b,h,w -------- -------- * 3 rdr011/(tdr011)[r/w] b,h,w ------- 0 00000000* 1 001910 h sacsr11[r/w] b,h,w 0 ---- 000 00000000 stmr11[r] b,h,w 00000000 00000000 001914 h stmcr11[r/w] b,h,w 00000000 00000000 D /(s cscr11/sfur11)[r/w] b,h, w -------- -------- * 3 * 4 001918 h D /(scstr311)/ (lamsr11) [r/w] b,h,w -------- * 3 D /(scstr211)/ (lamcr11) [r/w] b,h,w -------- * 3 D /(scstr111)/ (sflr111)[r/w] b,h,w -------- * 3 D /(scstr011)/ (sflr011)[r/w] b,h,w -------- * 3 00191c h D D /(scsfr211) [r/ w] b,h,w -------- * 3 D /(scsfr111) [r/w] b,h,w -------- * 3 D /(scsfr011) [r/w] b,h,w -------- * 3 001920 h D/(tbyte311)/ (lamesr11) [r/w] b,h,w -------- * 3 D/(tbyte211)/ (lamert11) [r/w] b,h,w -------- * 3 D/(tbyte111)/ (lamier11) [r/w] b,h,w -------- * 3 tbyte01 1/(lamrid 11)/(lamtid11) [r/w] b,h,w 00000000 001924 h bgr11[r/w] h, w 00000000 00000000 D /(ismk11)[r/w] b,h,w -------- * 2 D /(isba11)[r/w] b,h,w -------- * 2 001928 h fcr111[r/w] b,h,w --- 00100 fcr011[r/w] b,h,w - 0000000 fbyte11[r/w] b,h,w 00000000 00000 000 00192c h fticr11[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 108 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001930 h scr12/(ibcr12) [r/w] b,h,w 0 -- 00000 smr12 [r/w] b,h,w 000 - 00 - 0 ssr12 [r/w] b,h,w 0 - 000011 escr12/(ibsr12) [r/w] b,h,w 00000000 multi - uart12 *1: byte access is possible only for access to low er 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 001934 h D /( rdr112/(tdr112))[r/w] b,h,w -------- -------- * 3 rdr012/(tdr012)[r/w] b,h,w ------- 0 00000000* 1 001938 h sacsr12[r/w] b,h,w 0 ---- 000 00000000 stmr12[r] b,h,w 00000000 00000000 00193c h stmcr12[r/w] b,h,w 00000000 00000000 D / (scscr12/sfur12)[r/w] b,h,w -------- -------- * 3 * 4 0019 40 h D /(scstr312)/ (lamsr12) [r/w] b,h,w -------- * 3 D /(scstr212)/ (lamcr12) [r/w] b,h,w -------- * 3 D /(scstr112)/(sflr11 2) [r/w] b,h,w -------- * 3 D /(scstr012)/(sflr01 2) [r/w] b,h,w -------- * 3 001944 h D D /(scsfr212) [r/w] b,h,w -------- * 3 D /(scsfr112) [r/w] b,h,w -------- * 3 D /(scsfr012) [r/w] b,h,w -------- * 3 001948 h D/(tbyte312)/ (lamesr12) [r/w] b,h,w -------- * 3 D/(tbyte212)/ (lamert12) [r/w] b,h,w -------- * 3 D/(tbyte112)/ (lamier12) [r/w] b,h,w -------- * 3 tbyte012/(lamrid 12)/(lamtid12) [r/w] b,h, w 00000000 00194c h bgr12[r/w] h,w 00000000 00000000 D /(ismk12) [r/w] b,h,w -------- * 2 D /(isba12) [r/w] b,h,w -------- * 2 001950 h fcr112 [r/w] b,h,w --- 00100 fcr012 [r/w] b,h,w - 0000000 fbyte12[r/w] b,h,w 00000000 00000000 001954 h fticr12[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 1 09 confidential address address offset value / register name block +0 +1 +2 +3 001958 h scr13/(ibcr13) [r/w] b,h,w 0 -- 00000 smr13 [r/w] b,h,w 000 - 00 - 0 ssr13 [r/w] b,h,w 0 - 000011 escr13/(ibsr13) [r/w] b,h,w 00000000 multi - uart13 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 00195c h D /(rd r113/(tdr113))[r/w] b,h,w -------- -------- * 3 rdr013/(tdr01 3)[r/w] b,h,w ------- 0 00000000* 1 001960 h sacsr13[r/w] b,h,w 0 ---- 000 00000000 stmr13[r] b,h,w 00000000 00000000 001964 h stmcr13[r/w] b,h,w 00000000 00000000 D /(sc scr13/sfur13)[r/w] b,h,w -------- -------- * 3 * 4 001968 h D /(scstr313)/ (lamsr13) [r/w] b,h,w -------- * 3 D /(scstr213)/ (lamcr13) [r/w] b,h,w -------- * 3 D /(scstr113)/(sflr11 3) [r/w] b,h,w -------- * 3 D /(scstr013)/(sflr01 3) [r/w] b,h,w -------- * 3 00196c h D D /(scsfr213) [r/w] b,h,w -------- * 3 D /(scsfr113) [r/w] b,h,w -------- * 3 D /(scsfr0 13) [r/w] b,h,w -------- * 3 001970 h D/(tbyte313)/ (lamesr13) [r/w] b,h,w -------- * 3 D/(tbyte213)/ (lamert13) [r/w] b,h,w -------- * 3 D/(tbyte113)/ (lamier13) [r/w] b,h,w -------- * 3 tbyte013/(lamrid 13)/(lamtid13) [r/w] b,h,w 00000000 001974 h bgr13[r/w] h, w 00000000 00000000 D /(ismk13) [r/w] b,h,w -------- * 2 D /(isba13) [r/w] b,h,w -------- * 2 001978 h fcr113 [r/w] b,h,w --- 00100 fcr013 [r/w] b,h,w - 0000000 fbyte13[r/w] b,h,w 00000000 00000000 00197c h fticr13[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t 110 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001980 h sc r14/(ibcr14) [r/w] b,h,w 0 -- 00000 smr14 [r/w] b,h,w 000 - 00 - 0 ssr14 [r/w] b,h,w 0 - 000011 escr14/(ibsr14) [r/w] b,h,w 00000000 multi - uart14 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately aft er reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 001984 h D /(rd r114/(tdr114))[r/w] b,h,w -------- -------- * 3 rdr014/(tdr014)[r/w] b,h,w ------- 0 00000000* 1 001988 h sacsr14[r/w] b,h,w 0 ---- 000 00000000 stmr14[r] b,h,w 00000000 00000000 00198c h stmcr14[r/w] b,h,w 00000000 00000000 D /(sc scr14/sfur14)[r/w] b,h, w -------- -------- * 3 * 4 001990 h D /(scstr314)/ (lamsr14) [r/w] b,h,w -------- * 3 D /(scstr214)/ (lamcr14) [r/w] b,h,w -------- * 3 D /(scstr114)/(sflr11 4) [r/w] b,h,w -------- * 3 D /(scstr014)/(sflr01 4) [r/w] b,h,w -------- * 3 001994 h D D /(scsfr214) [r/w] b,h,w -------- * 3 D /(scsfr114) [r/w] b,h,w -------- * 3 D /(scsfr014) [r/w] b,h,w -------- * 3 001998 h D/(tbyte314)/ (lamesr14) [r/w] b,h,w -------- * 3 D/(tbyte214)/ (lamert14) [r/w] b,h,w -------- * 3 D/(tbyte114)/ (lamier14) [r/w] b,h,w -------- * 3 tbyte014/( lamrid 14)/(lamtid14) [r/w] b,h,w 00000000 00199c h bgr14[r/w] h,w 00000000 00000000 D /(ismk14) [r/w] b,h,w -------- * 2 D /(isba14) [r/w] b,h,w -------- * 2 0019a0 h fcr114 [r/w] b,h,w --- 00100 fcr014 [r/w] b,h,w - 0000000 fbyte14[r/w] b,h,w 00000000 0000000 0 0019a4 h fticr14[r/w] b,h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 111 confidential address address offset value / register name block +0 +1 +2 +3 0019a8 h scr15/(ibcr15) [r/w] b,h,w 0 -- 00000 smr15 [r/w] b,h,w 000 - 00 - 0 ssr15 [r/w] b,h,w 0 - 000011 escr15/(ibsr15) [r/w] b,h,w 00000000 multi - uart15 *1: byte access is possible only for access to lower 8 bits. *2: reserved because i 2 c mode is not set immediately after reset. *3: reserved because csio mode is not set immediately after reset. *4: reserved because lin2.1 mode is not set immediately after reset. 0019ac h D /(rdr1 15/(tdr115))[r/w] b,h,w -- ------ -------- * 3 rdr015/(tdr015)[r/w] b,h,w ------- 0 00000000* 1 0019b0 h sacsr15[r/w] b,h,w 0 ---- 000 00000000 stmr15[r] b,h,w 00000000 00000000 0019b4 h stmcr15[r/w] b,h,w 00000000 00000000 D /(sc scr15/sfur15)[r/w] b,h,w -------- -------- * 3 * 4 0019b8 h D /(scstr315)/ (lamsr15) [r/w] b,h,w -------- * 3 D /(scstr215)/ (lamcr15) [r/w] b,h,w -------- * 3 D /(scstr115)/(sflr11 5) [r/w] b,h,w -------- * 3 D /(scstr015)/(sflr01 5) [r/w] b,h,w -------- * 3 0019bc h D D /(scsfr215) [r/w] b,h,w -------- * 3 D /(scsfr115) [r /w] b,h,w -------- * 3 D /(scsfr015) [r/w] b,h,w -------- * 3 0019c0 h D/(tbyte315)/ (lamesr15) [r/w] b,h,w -------- * 3 D/(tbyte215)/ (lamert15) [r/w] b,h,w -------- * 3 D/(tbyte115)/ (lamier15) [r/w] b,h,w -------- * 3 tbyte015/(lamrid 15)/(lamtid15) [r/w] b,h,w 0 0000000 0019c4 h bgr15[r/w] h,w 00000000 00000000 D /(ismk15) [r/w] b,h,w -------- * 2 D /(isba15) [r/w] b,h,w -------- * 2 0019c8 h fcr115 [r/w] b,h,w --- 00100 fcr015 [r/w] b,h,w - 0000000 fbyte15[r/w] b,h,w 00000000 00000000 0019cc h fticr15[r/w] b,h,w 000 00000 00000000 D D d a t a s h e e t 112 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0019d0 h gtrs40 [r/w] b,h,w - 0000000 - 0000000 gtrs41 [r/w] b,h,w - 0000000 - 0000000 ppg controller 0019d4 h gtrs42 [r/w] b,h,w - 0000000 - 0000000 gtrs43 [r/w] b,h,w - 0000000 - 0000000 0019d8 h gtren4 [r/w] h,w 00000000 00000000 gtren5 [r/ w] h,w -------- 00000000 0019dc h D gatec0 [r/w] b,h,w ------ 00 D gatec2 [r/w] b,h,w ------ 00 ppg gate control 0019e0 h D gatec4 [r/w] b,h,w ------ 00 D D 0019e4 h D D D D reserved 0019e8 h gtrs0 [r/w] b,h,w - 0000000 - 0000000 gtrs1 [r/w] b,h,w - 0000000 - 0000000 ppg controller 0019ec h gtrs2 [r/w] b,h,w - 0000000 - 0000000 gtrs3 [r/w] b,h,w - 0000000 - 0000000 0019f0 h gtrs4 [r/w] b,h,w - 0000000 - 0000000 gtrs5 [r/w] b,h,w - 0000000 - 0000000 0019f4 h gtrs6 [r/w] b,h,w - 0000000 - 0000000 gtrs7 [r/w] b,h,w - 000 0000 - 0000000 0019f8 h gtrs8 [r/w] b,h,w - 0000000 - 0000000 gtrs9 [r/w] b,h,w - 0000000 - 0000000 0019fc h gtrs10 [r/w] b,h,w - 0000000 - 0000000 gtrs11 [r/w] b,h,w - 0000000 - 0000000 001a00 h gtrs12 [r/w] b,h,w - 0000000 - 0000000 gtrs13 [r/w] b,h,w - 0000000 - 0000000 001a04 h gtrs14 [r/w] b,h,w - 0000000 - 0000000 gtrs15 [r/w] b,h,w - 0000000 - 0000000 001a08 h gtrs16 [r/w] b,h,w - 0000000 - 0000000 gtrs17 [r/w] b,h,w - 0000000 - 0000000 001a0c h gtrs18 [r/w] b,h,w - 0000000 - 0000000 gtrs19 [r/w] b,h,w - 0000000 - 0000 000 001a10 h gtrs20 [r/w] b,h,w - 0000000 - 0000000 gtrs21 [r/w] b,h,w - 0000000 - 0000000 001a14 h gtrs22 [r/w] b,h,w - 0000000 - 0000000 gtrs23 [r/w] b,h,w - 0000000 - 0000000 001a18 h gtrs24 [r/w] b,h,w - 0000000 - 0000000 gtrs25 [r/w] b,h,w - 0000000 - 0000000 001a1c h gtrs26 [r/w] b,h,w - 0000000 - 0000000 gtrs27 [r/w] b,h,w - 0000000 - 0000000 001a20 h gtrs28 [r/w] b,h,w - 0000000 - 0000000 gtrs29 [r/w] b,h,w - 0000000 - 0000000 001a24 h gtrs30 [r/w] b,h,w - 0000000 - 0000000 gtrs31 [r/w] b,h,w - 0000000 - 0000000 0 01a28 h gtrs32 [r/w] b,h,w - 0000000 - 0000000 gtrs33 [r/w] b,h,w - 0000000 - 0000000 001a2c h gtrs34 [r/w] b,h,w - 0000000 - 0000000 gtrs35 [r/w] b,h,w - 0000000 - 0000000 001a30 h gtrs36 [r/w] b,h,w - 0000000 - 0000000 gtrs37 [r/w] b,h,w - 0000000 - 0000000 001a3 4 h gtrs38 [r/w] b,h,w - 0000000 - 0000000 gtrs39 [r/w] b,h,w - 0000000 - 0000000 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 113 confidential address address offset value / register name block +0 +1 +2 +3 001a38 h gtren0 [r/w] h,w 00000000 00000000 gtren1 [r/w] h,w 00000000 00000000 ppg controller 001a3c h gtren2 [r/w] h,w 00000000 00000000 gtren3 [r/w] h,w 00000000 00000000 001 a40 h pcn0 [r/w] b,h,w 00000000 000000 - 0 pcsr0 [w] h,w xxxxxxxx xxxxxxxx ppg0 (note) for communication 001a44 h pdut0 [w] h,w xxxxxxxx xxxxxxxx ptmr0 [r] h,w 11111111 11111111 001a48 h pcn200 [r/w] b,h,w -- 000000 ----- 110 psdr0 [r/w] h,w 00000000 00000000 001a4c h ptpc0 [r/w] h,w 00000000 00000000 pcmdwd0 [r/w] b,h,w -------- ---- 0000 001a50 h phcsr0 [w] h,w xxxxxxxx xxxxxxxx plcsr0 [w] h,w xxxxxxxx xxxxxxxx 001a54 h phdut0 [w] h,w xxxxxxxx xxxxxxxx pldut0 [w] h,w xxxxxxxx xxxxxxxx 001a58 h pcmddt0 [r/w ] h,w 00000000 00000000 D D 001a5c h pcn1 [r/w] b,h,w 00000000 000000 - 0 pcsr1 [w] h,w xxxxxxxx xxxxxxxx ppg1 (note) for communication 001a60 h pdut1 [w] h,w xxxxxxxx xxxxxxxx ptmr1 [r] h,w 11111111 11111111 001a64 h pcn201 [r/w] b,h,w -- 000000 ----- 110 psdr1 [r/w] h,w 00000000 00000000 001a68 h ptpc1 [r/w] h,w 00000000 00000000 pcmdwd1 [r/w] b,h,w -------- ---- 0000 001a6c h phcsr1 [w] h,w xxxxxxxx xxxxxxxx plcsr1 [w] h,w xxxxxxxx xxxxxxxx 001a70 h phdut1 [w] h,w xxxxxxxx xxxxxxxx pldut1 [w] h,w xxxxxxxx xxxxxxxx 001a74 h pcm ddt1 [r/w] h,w 00000000 00000000 D D 001a78 h pcn2 [r/w] b,h,w 00000000 000000 - 0 pcsr2 [w] h,w xxxxxxxx xxxxxxxx ppg2 (note) for communication 001a7c h pdut2 [w] h,w xxxxxxxx xxxxxxxx ptmr2 [r] h,w 11111111 11111111 001a80 h pcn202 [r/w] b,h,w -- 000000 ----- 110 psdr2 [r/w] h,w 00000000 00000000 001a84 h ptpc2 [r/w] h,w 00000000 00000000 pcmdwd2 [r/w] b,h,w -------- ---- 0000 001a88 h phcsr2 [w] h,w xxxxxxxx xxxxxxxx plcsr2 [w] h,w xxxxxxxx xxxxxxxx 001a8c h phdut2 [w] h,w xxxxxxxx xxxxxxxx pldut2 [w] h,w xxxxxxxx xxxxxxxx 001a90 h pcm ddt2 [r/w] h,w 00000000 00000000 D D d a t a s h e e t 114 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001a94 h pcn3 [r/w] b,h,w 00000000 000000 - 0 pcsr3 [w] h,w xxxxxxxx xxxxxxxx ppg3 (note) for communication 001a98 h pdut3 [w] h,w xxxxxxxx xxxxxxxx ptmr3 [r] h,w 11111111 11111111 001a9c h pcn203 [r/w] b,h,w -- 000000 ----- 110 psdr3 [r/w] h,w 00000000 00000000 001aa0 h ptpc3 [r/w] h,w 00000000 00000000 pcmdwd3 [r/w] b,h,w -------- ---- 0000 001aa4 h phcsr3 [w] h,w xxxxxxxx xxxxxxxx plcsr3 [w] h,w xxxxxxxx xxxxxxxx 001aa8 h phdut3 [w] h,w xxxxxxxx xxxxxxxx pldut3 [w] h,w xxxxxxxx xxxxxxxx 001aac h pcm ddt3 [r/w] h,w 00000000 00000000 D D 001ab0 h pcn4 [r/w] b,h,w 00000000 000000 - 0 pcsr4 [w] h,w xxxxxxxx xxxxxxxx ppg4 001ab4 h pdut4 [w] h,w xxxxxxxx xxxxxxxx ptmr4 [r] h,w 11111111 11111111 001ab8 h pcn204 [r/w] b,h,w -- 000000 ----- 110 psdr4 [r/w] h,w 0 0000000 00000000 001abc h ptpc4 [r/w] h,w 00000000 00000000 D D 001ac0 h pcn5 [r/w] b,h,w 00000000 000000 - 0 pcsr5 [w] h,w xxxxxxxx xxxxxxxx ppg5 001ac4 h pdut5 [w] h,w xxxxxxxx xxxxxxxx ptmr5 [r] h,w 11111111 11111111 001ac8 h pcn205 [r/w] b,h,w -- 00000 0 ----- 110 psdr5 [r/w] h,w 00000000 00000000 001acc h ptpc5 [r/w] h,w 00000000 00000000 D D 001ad0 h pcn6 [r/w] b,h,w 00000000 000000 - 0 pcsr6 [w] h,w xxxxxxxx xxxxxxxx ppg6 001ad4 h pdut6 [w] h,w xxxxxxxx xxxxxxxx ptmr6 [r] h,w 11111111 11111111 001ad8 h pcn206 [r/w] b,h,w -- 000000 ----- 110 psdr6 [r/w] h,w 00000000 00000000 001adc h ptpc6 [r/w] h,w 00000000 00000000 D D 001ae0 h pcn7 [r/w] b,h,w 00000000 000000 - 0 pcsr7 [w] h,w xxxxxxxx xxxxxxxx ppg7 001ae4 h pdut7 [w] h,w xxxxxxxx xxxxxxxx ptmr7 [r] h, w 11111111 11111111 001ae8 h pcn207 [r/w] b,h,w -- 000000 ----- 110 psdr7 [r/w] h,w 00000000 00000000 001aec h ptpc7 [r/w] h,w 00000000 00000000 D D 001af0 h pcn8 [r/w] b,h,w 00000000 000000 - 0 pcsr8 [w] h,w xxxxxxxx xxxxxxxx ppg8 001af4 h pdut8 [w] h,w xx xxxxxx xxxxxxxx ptmr8 [r] h,w 11111111 11111111 001af8 h pcn208 [r/w] b,h,w -- 000000 ----- 110 psdr8 [r/w] h,w 00000000 00000000 001afc h ptpc8 [r/w] h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 115 confidential address address offset value / register name block +0 +1 +2 +3 001b00 h pcn9 [r/w] b,h,w 00000000 000000 - 0 pcsr9 [w] h,w xxxxxxxx xxxxxxxx pp g9 001b04 h pdut9 [w] h,w xxxxxxxx xxxxxxxx ptmr9 [r] h,w 11111111 11111111 001b08 h pcn209 [r/w] b,h,w -- 000000 ----- 110 psdr9 [r/w] h,w 00000000 00000000 001b0c h ptpc9 [r/w] h,w 00000000 00000000 D D 001b10 h pcn10 [r/w] b,h,w 00000000 000000 - 0 pcsr1 0 [w] h,w xxxxxxxx xxxxxxxx ppg10 001b14 h pdut10 [w] h,w xxxxxxxx xxxxxxxx ptmr10 [r] h,w 11111111 11111111 001b18 h pcn210 [r/w] b,h,w -- 000000 ----- 110 psdr10 [r/w] h,w 00000000 00000000 001b1c h ptpc10 [r/w] h,w 00000000 00000000 D D 001b20 h pcn11 [r/w] b,h,w 00000000 000000 - 0 pcsr11 [w] h,w xxxxxxxx xxxxxxxx ppg11 001b24 h pdut11 [w] h,w xxxxxxxx xxxxxxxx ptmr11 [r] h,w 11111111 11111111 001b28 h pcn211 [r/w] b,h,w -- 000000 ----- 110 psdr11 [r/w] h,w 00000000 00000000 001b2c h ptpc11 [r/w] h,w 000 00000 00000000 D D 001b30 h pcn12 [r/w] b,h,w 00000000 000000 - 0 pcsr12 [w] h,w xxxxxxxx xxxxxxxx ppg12 001b34 h pdut12 [w] h,w xxxxxxxx xxxxxxxx ptmr12 [r] h,w 11111111 11111111 001b38 h pcn212 [r/w] b,h,w -- 000000 ----- 110 psdr12 [r/w] h,w 00000000 0000 0000 001b3c h ptpc12 [r/w] h,w 00000000 00000000 D D 001b40 h pcn13 [r/w] b,h,w 00000000 000000 - 0 pcsr13 [w] h,w xxxxxxxx xxxxxxxx ppg13 001b44 h pdut13 [w] h,w xxxxxxxx xxxxxxxx ptmr13 [r] h,w 11111111 11111111 001b48 h pcn213 [r/w] b,h,w -- 000000 ---- - 110 psdr13 [r/w] h,w 00000000 00000000 001b4c h ptpc13 [r/w] h,w 00000000 00000000 D D 001b50 h pcn14 [r/w] b,h,w 00000000 000000 - 0 pcsr14 [w] h,w xxxxxxxx xxxxxxxx ppg14 001b54 h pdut14 [w] h,w xxxxxxxx xxxxxxxx ptmr14 [r] h,w 11111111 11111111 001b5 8 h pcn214 [r/w] b,h,w -- 000000 ----- 110 psdr14 [r/w] h,w 00000000 00000000 001b5c h ptpc14 [r/w] h,w 00000000 00000000 D D d a t a s h e e t 116 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001b60 h pcn15 [r/w] b,h,w 00000000 000000 - 0 pcsr15 [w] h,w xxxxxxxx xxxxxxxx ppg15 001b64 h pdut15 [w] h,w xxxxxxxx xxxxxxxx ptmr1 5 [r] h,w 11111111 11111111 001b68 h pcn215 [r/w] b,h,w -- 000000 ----- 110 psdr15 [r/w] h,w 00000000 00000000 001b6c h ptpc15 [r/w] h,w 00000000 00000000 D D 001b70 h pcn16 [r/w] b,h,w 00000000 000000 - 0 pcsr16 [w] h,w xxxxxxxx xxxxxxxx ppg16 001b74 h pdu t16 [w] h,w xxxxxxxx xxxxxxxx ptmr16 [r] h,w 11111111 11111111 001b78 h pcn216 [r/w] b,h,w -- 000000 ----- 110 psdr16 [r/w] h,w 00000000 00000000 001b7c h ptpc16 [r/w] h,w 00000000 00000000 D D 001b80 h pcn17 [r/w] b,h,w 00000000 000000 - 0 pcsr17 [w] h,w x xxxxxxx xxxxxxxx ppg17 001b84 h pdut17 [w] h,w xxxxxxxx xxxxxxxx ptmr17 [r] h,w 11111111 11111111 001b88 h pcn217 [r/w] b,h,w -- 000000 ----- 110 psdr17 [r/w] h,w 00000000 00000000 001b8c h ptpc17 [r/w] h,w 00000000 00000000 D D 001b90 h pcn18 [r/w] b,h,w 00000000 000000 - 0 pcsr18 [w] h,w xxxxxxxx xxxxxxxx ppg18 001b94 h pdut18 [w] h,w xxxxxxxx xxxxxxxx ptmr18 [r] h,w 11111111 11111111 001b98 h pcn218 [r/w] b,h,w -- 000000 ----- 110 psdr18 [r/w] h,w 00000000 00000000 001b9c h ptpc18 [r/w] h,w 00000000 00000 000 D D 001ba0 h pcn19 [r/w] b,h,w 00000000 000000 - 0 pcsr19 [w] h,w xxxxxxxx xxxxxxxx ppg19 001ba4 h pdut19 [w] h,w xxxxxxxx xxxxxxxx ptmr19 [r] h,w 11111111 11111111 001ba8 h pcn219 [r/w] b,h,w -- 000000 ----- 110 psdr19 [r/w] h,w 00000000 00000000 001b ac h ptpc19 [r/w] h,w 00000000 00000000 D D 001bb0 h pcn20 [r/w] b,h,w 00000000 000000 - 0 pcsr20 [w] h,w xxxxxxxx xxxxxxxx ppg20 001bb4 h pdut20 [w] h,w xxxxxxxx xxxxxxxx ptmr20 [r] h,w 11111111 11111111 001bb8 h pcn220 [r/w] b,h,w -- 000000 ----- 110 psdr20 [r/w] h,w 00000000 00000000 001bbc h ptpc20 [r/w] h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 117 confidential address address offset value / register name block +0 +1 +2 +3 001bc0 h pcn21 [r/w] b,h,w 00000000 000000 - 0 pcsr21 [w] h,w xxxxxxxx xxxxxxxx ppg21 001bc4 h pdut21 [w] h,w xxxxxxxx xxxxxxxx ptmr21 [r] h,w 11111111 11111111 001bc8 h pcn221 [ r/w] b,h,w -- 000000 ----- 110 psdr21 [r/w] h,w 00000000 00000000 001bcc h ptpc21 [r/w] h,w 00000000 00000000 D D 001bd0 h pcn22 [r/w] b,h,w 00000000 000000 - 0 pcsr22 [w] h,w xxxxxxxx xxxxxxxx ppg22 001bd4 h pdut22 [w] h,w xxxxxxxx xxxxxxxx ptmr22 [r] h,w 1 1111111 11111111 001bd8 h pcn222 [r/w] b,h,w -- 000000 ----- 110 psdr22 [r/w] h,w 00000000 00000000 001bdc h ptpc22 [r/w] h,w 00000000 00000000 D D 001be0 h pcn23 [r/w] b,h,w 00000000 000000 - 0 pcsr23 [w] h,w xxxxxxxx xxxxxxxx ppg23 001be4 h pdut23 [w] h,w xxxxxxxx xxxxxxxx ptmr23 [r] h,w 11111111 11111111 001be8 h pcn223 [r/w] b,h,w -- 000000 ----- 110 psdr23 [r/w] h,w 00000000 00000000 001bec h ptpc23 [r/w] h,w 00000000 00000000 D D 001bf0 h pcn24 [r/w] b,h,w 00000000 000000 - 0 pcsr24 [w] h,w xxxxxxxx xxx xxxxx ppg24 001bf4 h pdut24 [w] h,w xxxxxxxx xxxxxxxx ptmr24 [r] h,w 11111111 11111111 001bf8 h pcn224 [r/w] b,h,w -- 000000 ----- 110 psdr24 [r/w] h,w 00000000 00000000 001bfc h ptpc24 [r/w] h,w 00000000 00000000 D D 001c00 h pcn25 [r/w] b,h,w 00000000 0 00000 - 0 pcsr25 [w] h,w xxxxxxxx xxxxxxxx ppg25 001c04 h pdut25 [w] h,w xxxxxxxx xxxxxxxx ptmr25 [r] h,w 11111111 11111111 001c08 h pcn225 [r/w] b,h,w -- 000000 ----- 110 psdr25 [r/w] h,w 00000000 00000000 001c0c h ptpc25 [r/w] h,w 00000000 00000000 D D 0 01c10 h pcn26 [r/w] b,h,w 00000000 000000 - 0 pcsr26 [w] h,w xxxxxxxx xxxxxxxx ppg26 001c14 h pdut26 [w] h,w xxxxxxxx xxxxxxxx ptmr26 [r] h,w 11111111 11111111 001c18 h pcn226 [r/w] b,h,w -- 000000 ----- 110 psdr26 [r/w] h,w 00000000 00000000 001c1c h ptpc26 [r/w] h,w 00000000 00000000 D D d a t a s h e e t 118 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001c20 h pcn27 [r/w] b,h,w 00000000 000000 - 0 pcsr27 [w] h,w xxxxxxxx xxxxxxxx ppg27 001c24 h pdut27 [w] h,w xxxxxxxx xxxxxxxx ptmr27 [r] h,w 11111111 11111111 001c28 h pcn227 [r/w] b,h,w -- 000000 ----- 110 psdr27 [r/w] h,w 00000000 00000000 001c2c h ptpc27 [r/w] h,w 00000000 00000000 D D 001c30 h pcn28 [r/w] b,h,w 00000000 000000 - 0 pcsr28 [w] h,w xxxxxxxx xxxxxxxx ppg28 001c34 h pdut28 [w] h,w xxxxxxxx xxxxxxxx ptmr28 [r] h,w 11111111 11111111 001c38 h pcn228 [r/w] b,h,w -- 000000 ----- 110 psdr28 [r/w] h,w 00000000 00000000 001c3c h ptpc28 [r/w] h,w 00000000 00000000 D D 001c40 h pcn29 [r/w] b,h,w 00000000 000000 - 0 pcsr29 [w] h,w xxxxxxxx xxxxxxxx ppg29 001c44 h pdut29 [w] h,w xxxxxxxx xxxxxxxx ptmr29 [r] h,w 11111111 111 11111 001c48 h pcn229 [r/w] b,h,w -- 000000 ----- 110 psdr29 [r/w] h,w 00000000 00000000 001c4c h ptpc29 [r/w] h,w 00000000 00000000 D D 001c50 h pcn30 [r/w] b,h,w 00000000 000000 - 0 pcsr30 [w] h,w xxxxxxxx xxxxxxxx ppg30 001c54 h pdut30 [w] h,w xxxxxxxx x xxxxxxx ptmr30 [r] h,w 11111111 11111111 001c58 h pcn230 [r/w] b,h,w -- 000000 ----- 110 psdr30 [r/w] h,w 00000000 00000000 001c5c h ptpc30 [r/w] h,w 00000000 00000000 D D 001c60 h pcn31 [r/w] b,h,w 00000000 000000 - 0 pcsr31 [w] h,w xxxxxxxx xxxxxxxx ppg31 001c64 h pdut31 [w] h,w xxxxxxxx xxxxxxxx ptmr31 [r] h,w 11111111 11111111 001c68 h pcn231 [r/w] b,h,w -- 000000 ----- 110 psdr31 [r/w] h,w 00000000 00000000 001c6c h ptpc31 [r/w] h,w 00000000 00000000 D D 001c70 h pcn32 [r/w] b,h,w 00000000 000000 - 0 pcs r32 [w] h,w xxxxxxxx xxxxxxxx ppg32 001c74 h pdut32 [w] h,w xxxxxxxx xxxxxxxx ptmr32 [r] h,w 11111111 11111111 001c78 h pcn232 [r/w] b,h,w -- 000000 ----- 110 psdr32 [r/w] h,w 00000000 00000000 001c7c h ptpc32 [r/w] h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 119 confidential address address offset value / register name block +0 +1 +2 +3 001c80 h pcn3 3 [r/w] b,h,w 00000000 000000 - 0 pcsr33 [w] h,w xxxxxxxx xxxxxxxx ppg33 001c84 h pdut33 [w] h,w xxxxxxxx xxxxxxxx ptmr33 [r] h,w 11111111 11111111 001c88 h pcn233 [r/w] b,h,w -- 000000 ----- 110 psdr33 [r/w] h,w 00000000 00000000 001c8c h ptpc33 [r/w] h,w 0 0000000 00000000 D D 001c90 h pcn34 [r/w] b,h,w 00000000 000000 - 0 pcsr34 [w] h,w xxxxxxxx xxxxxxxx ppg34 001c94 h pdut34 [w] h,w xxxxxxxx xxxxxxxx ptmr34 [r] h,w 11111111 11111111 001c98 h pcn234 [r/w] b,h,w -- 000000 ----- 110 psdr34 [r/w] h,w 00000000 00 000000 001c9c h ptpc34 [r/w] h,w 00000000 00000000 D D 001ca0 h pcn35 [r/w] b,h,w 00000000 000000 - 0 pcsr35 [w] h,w xxxxxxxx xxxxxxxx ppg35 001ca4 h pdut35 [w] h,w xxxxxxxx xxxxxxxx ptmr35 [r] h,w 11111111 11111111 001ca8 h pcn235 [r/w] b,h,w -- 000000 -- --- 110 psdr35 [r/w] h,w 00000000 00000000 001cac h ptpc35 [r/w] h,w 00000000 00000000 D D 001cb0 h pcn36 [r/w] b,h,w 00000000 000000 - 0 pcsr36 [w] h,w xxxxxxxx xxxxxxxx ppg36 001cb4 h pdut36 [w] h,w xxxxxxxx xxxxxxxx ptmr36 [r] h,w 11111111 11111111 001 cb8 h pcn236 [r/w] b,h,w -- 000000 ----- 110 psdr36 [r/w] h,w 00000000 00000000 001cbc h ptpc36 [r/w] h,w 00000000 00000000 D D 001cc0 h pcn37 [r/w] b,h,w 00000000 000000 - 0 pcsr37 [w] h,w xxxxxxxx xxxxxxxx ppg37 001cc4 h pdut37 [w] h,w xxxxxxxx xxxxxxxx ptm r37 [r] h,w 11111111 11111111 001cc8 h pcn237 [r/w] b,h,w -- 000000 ----- 110 psdr37 [r/w] h,w 00000000 00000000 001ccc h ptpc37 [r/w] h,w 00000000 00000000 D D 001cd0 h pcn38 [r/w] b,h,w 00000000 000000 - 0 pcsr38 [w] h,w xxxxxxxx xxxxxxxx ppg38 001cd4 h p dut38 [w] h,w xxxxxxxx xxxxxxxx ptmr38 [r] h,w 11111111 11111111 001cd8 h pcn238 [r/w] b,h,w -- 000000 ----- 110 psdr38 [r/w] h,w 00000000 00000000 001cdc h ptpc38 [r/w] h,w 00000000 00000000 D D d a t a s h e e t 120 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001ce0 h pcn39 [r/w] b,h,w 00000000 000000 - 0 pcsr39 [w] h,w xxxxxxxx xxxxxxxx ppg39 001ce4 h pdut39 [w] h,w xxxxxxxx xxxxxxxx ptmr39 [r] h,w 11111111 11111111 001ce8 h pcn239 [r/w] b,h,w -- 000000 ----- 110 psdr39 [r/w] h,w 00000000 00000000 001cec h ptpc39 [r/w] h,w 00000000 00000000 D D 001cf0 h pcn40 [r/w] b,h ,w 00000000 000000 - 0 pcsr40 [w] h,w xxxxxxxx xxxxxxxx ppg40 001cf4 h pdut40 [w] h,w xxxxxxxx xxxxxxxx ptmr40 [r] h,w 11111111 11111111 001cf8 h pcn240 [r/w] b,h,w -- 000000 ----- 110 psdr40 [r/w] h,w 00000000 00000000 001cfc h ptpc40 [r/w] h,w 00000000 000 00000 D D 001d00 h pcn41 [r/w] b,h,w 00000000 000000 - 0 pcsr41 [w] h,w xxxxxxxx xxxxxxxx ppg41 001d04 h pdut41 [w] h,w xxxxxxxx xxxxxxxx ptmr41 [r] h,w 11111111 11111111 001d08 h pcn241 [r/w] b,h,w -- 000000 ----- 110 psdr41 [r/w] h,w 00000000 00000000 00 1d0c h ptpc41 [r/w] h,w 00000000 00000000 D D 001d10 h pcn42 [r/w] b,h,w 00000000 000000 - 0 pcsr42 [w] h,w xxxxxxxx xxxxxxxx ppg42 001d14 h pdut42 [w] h,w xxxxxxxx xxxxxxxx ptmr42 [r] h,w 11111111 11111111 001d18 h pcn242 [r/w] b,h,w -- 000000 ----- 110 psdr 42 [r/w] h,w 00000000 00000000 001d1c h ptpc42 [r/w] h,w 00000000 00000000 D D 001d20 h pcn43 [r/w] b,h,w 00000000 000000 - 0 pcsr43 [w] h,w xxxxxxxx xxxxxxxx ppg43 001d24 h pdut43 [w] h,w xxxxxxxx xxxxxxxx ptmr43 [r] h,w 11111111 11111111 001d28 h pcn243 [r/w] b,h,w -- 000000 ----- 110 psdr43 [r/w] h,w 00000000 00000000 001d2c h ptpc43 [r/w] h,w 00000000 00000000 D D 001d30 h pcn44 [r/w] b,h,w 00000000 000000 - 0 pcsr44 [w] h,w xxxxxxxx xxxxxxxx ppg44 001d34 h pdut44 [w] h,w xxxxxxxx xxxxxxxx ptmr44 [r] h,w 11111111 11111111 001d38 h pcn244 [r/w] b,h,w -- 000000 ----- 110 psdr44 [r/w] h,w 00000000 00000000 001d3c h ptpc44 [r/w] h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 121 confidential address address offset value / register name block +0 +1 +2 +3 001d40 h pcn45 [r/w] b,h,w 00000000 000000 - 0 pcsr45 [w] h,w xxxxxxxx xxxxxxxx ppg45 001d44 h pdut45 [w] h ,w xxxxxxxx xxxxxxxx ptmr45 [r] h,w 11111111 11111111 001d48 h pcn245 [r/w] b,h,w -- 000000 ----- 110 psdr45 [r/w] h,w 00000000 00000000 001d4c h ptpc45 [r/w] h,w 00000000 00000000 D D 001d50 h pcn46 [r/w] b,h,w 00000000 000000 - 0 pcsr46 [w] h,w xxxxxxxx x xxxxxxx ppg46 001d54 h pdut46 [w] h,w xxxxxxxx xxxxxxxx ptmr46 [r] h,w 11111111 11111111 001d58 h pcn246 [r/w] b,h,w -- 000000 ----- 110 psdr46 [r/w] h,w 00000000 00000000 001d5c h ptpc46 [r/w] h,w 00000000 00000000 D D 001d60 h pcn47 [r/w] b,h,w 00000000 000000 - 0 pcsr47 [w] h,w xxxxxxxx xxxxxxxx ppg47 001d64 h pdut47 [w] h,w xxxxxxxx xxxxxxxx ptmr47 [r] h,w 11111111 11111111 001d68 h pcn247 [r/w] b,h,w -- 000000 ----- 110 psdr47 [r/w] h,w 00000000 00000000 001d6c h ptpc47 [r/w] h,w 00000000 00000000 D D 001d70 h pcn48 [r/w] b,h,w 00000000 000000 - 0 pcsr48 [w] h,w xxxxxxxx xxxxxxxx ppg48 001d74 h pdut48 [w] h,w xxxxxxxx xxxxxxxx ptmr48 [r] h,w 11111111 11111111 001d78 h pcn248 [r/w] b,h,w -- 000000 ----- 110 psdr48 [r/w] h,w 00000000 00000000 001d7c h ptpc 48 [r/w] h,w 00000000 00000000 D D 001d80 h pcn49 [r/w] b,h,w 00000000 000000 - 0 pcsr49 [w] h,w xxxxxxxx xxxxxxxx ppg49 001d84 h pdut49 [w] h,w xxxxxxxx xxxxxxxx ptmr49 [r] h,w 11111111 11111111 001d88 h pcn249 [r/w] b,h,w -- 000000 ----- 110 psdr49 [r/w] h ,w 00000000 00000000 001d8c h ptpc49 [r/w] h,w 00000000 00000000 D D 001d90 h pcn50 [r/w] b,h,w 00000000 000000 - 0 pcsr50 [w] h,w xxxxxxxx xxxxxxxx ppg50 001d94 h pdut50 [w] h,w xxxxxxxx xxxxxxxx ptmr50 [r] h,w 11111111 11111111 001d98 h pcn250 [r/w] b,h ,w -- 000000 ----- 110 psdr50 [r/w] h,w 00000000 00000000 001d9c h ptpc50 [r/w] h,w 00000000 00000000 D D d a t a s h e e t 122 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001da0 h pcn51 [r/w] b,h,w 00000000 000000 - 0 pcsr51 [w] h,w xxxxxxxx xxxxxxxx ppg51 001da4 h pdut51 [w] h,w xxxxxxxx xxxxxxxx ptmr51 [r] h,w 11111111 11111111 001da8 h pcn251 [r/w] b,h,w -- 000000 ----- 110 psdr51 [r/w] h,w 00000000 00000000 001dac h ptpc51 [r/w] h,w 00000000 00000000 D D 001db0 h pcn52 [r/w] b,h,w 00000000 000000 - 0 pcsr52 [w] h,w xxxxxxxx xxxxxxxx ppg52 001db4 h pdut52 [w] h,w xxxxxxx x xxxxxxxx ptmr52 [r] h,w 11111111 11111111 001db8 h pcn252 [r/w] b,h,w -- 000000 ----- 110 psdr52 [r/w] h,w 00000000 00000000 001dbc h ptpc52 [r/w] h,w 00000000 00000000 D D 001dc0 h pcn53 [r/w] b,h,w 00000000 000000 - 0 pcsr53 [w] h,w xxxxxxxx xxxxxxxx pp g53 001dc4 h pdut53 [w] h,w xxxxxxxx xxxxxxxx ptmr53 [r] h,w 11111111 11111111 001dc8 h pcn253 [r/w] b,h,w -- 000000 ----- 110 psdr53 [r/w] h,w 00000000 00000000 001dcc h ptpc53 [r/w] h,w 00000000 00000000 D D 001dd0 h pcn54 [r/w] b,h,w 00000000 000000 - 0 pcsr54 [w] h,w xxxxxxxx xxxxxxxx ppg54 001dd4 h pdut54 [w] h,w xxxxxxxx xxxxxxxx ptmr54 [r] h,w 11111111 11111111 001dd8 h pcn254 [r/w] b,h,w -- 000000 ----- 110 psdr54 [r/w] h,w 00000000 00000000 001ddc h ptpc54 [r/w] h,w 00000000 00000000 D D 001de0 h p cn55 [r/w] b,h,w 00000000 000000 - 0 pcsr55 [w] h,w xxxxxxxx xxxxxxxx ppg55 001de4 h pdut55 [w] h,w xxxxxxxx xxxxxxxx ptmr55 [r] h,w 11111111 11111111 001de8 h pcn255 [r/w] b,h,w -- 000000 ----- 110 psdr55 [r/w] h,w 00000000 00000000 001dec h ptpc55 [r/w] h, w 00000000 00000000 D D 001df0 h pcn56 [r/w] b,h,w 00000000 000000 - 0 pcsr56 [w] h,w xxxxxxxx xxxxxxxx ppg56 001df4 h pdut56 [w] h,w xxxxxxxx xxxxxxxx ptmr56 [r] h,w 11111111 11111111 001df8 h pcn256 [r/w] b,h,w -- 000000 ----- 110 psdr56 [r/w] h,w 00000000 00000000 001dfc h ptpc56 [r/w] h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 123 confidential address address offset value / register name block +0 +1 +2 +3 001e00 h pcn57 [r/w] b,h,w 00000000 000000 - 0 pcsr57 [w] h,w xxxxxxxx xxxxxxxx ppg57 001e04 h pdut57 [w] h,w xxxxxxxx xxxxxxxx ptmr57 [r] h,w 11111111 11111111 001e08 h pcn257 [r/w] b,h,w -- 000000 ----- 110 psdr57 [r/w] h,w 00000000 00000000 001e0c h ptpc57 [r/w] h,w 00000000 00000000 D D 001e10 h pcn58 [r/w] b,h,w 00000000 000000 - 0 pcsr58 [w] h,w xxxxxxxx xxxxxxxx ppg58 001e14 h pdut58 [w] h,w xxxxxxxx xxxxxxxx ptmr58 [r] h,w 11111111 11111111 001e18 h pcn258 [r/w] b,h,w -- 000000 ----- 110 psdr58 [r/w] h,w 00000000 00000000 001e1c h ptpc58 [r/w] h,w 00000000 00000000 D D 001e20 h pcn59 [r/w] b,h,w 00000000 000000 - 0 pcsr59 [w] h,w xxxxxxxx xxxxxxxx ppg59 001e24 h pdut59 [w] h,w xxxxxxxx xxxxxxxx ptmr59 [r] h,w 11111111 11111111 001e28 h pcn259 [r/w] b,h,w -- 000000 ----- 110 psdr59 [r/w] h,w 00000000 00000000 001e2c h ptpc59 [r/w] h,w 00000000 00000000 D D 001e30 h pcn60 [r/w] b,h,w 00000000 000000 - 0 pcsr60 [w] h,w xxxxxxxx xxxxxxxx ppg60 001e34 h pdut60 [w] h,w xxxxxxxx xxxxxxxx ptmr60 [r] h,w 11111111 11111111 001e38 h pcn260 [r/w] b,h,w -- 000000 ----- 110 psdr60 [r/w] h,w 00000000 00000000 001e3c h ptpc60 [r/w] h,w 00000000 00000000 D D 001e40 h pcn61 [r/w] b,h,w 00000000 000000 - 0 pcsr61 [w] h,w xxxxxxxx xxxxxxxx ppg61 001e44 h pdut61 [w] h,w xxxxxxxx xxxxxxxx ptmr61 [r] h,w 11111111 11111111 001e48 h pcn261 [r/w] b,h,w -- 000000 ----- 110 psdr61 [r/w] h,w 00000000 00000000 001e4c h ptpc61 [r/w] h,w 00000000 00000000 D D 001e50 h pcn62 [r/w] b,h,w 00000000 000000 - 0 pcsr62 [w] h,w xxxxxxxx xxxxxxxx ppg62 001e54 h pdut62 [w] h,w xxxxxxxx xxxxxxxx ptmr62 [r] h,w 11111111 11111111 001e58 h pcn262 [r/w] b,h,w -- 000000 ----- 110 psdr62 [r/w] h,w 00000000 00000000 001e5c h ptpc62 [r/w] h,w 00000000 00000000 D D d a t a s h e e t 124 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001e60 h pcn63 [r/w] b,h,w 00000000 000000 - 0 pcsr63 [w] h,w xxxxxxxx xxxxxxxx ppg63 001e64 h pdut63 [w] h,w xxxxxxxx xxxxxxxx ptmr63 [r] h,w 11111111 11111111 001e68 h pcn263 [r/w] b,h,w -- 000000 ----- 110 psdr63 [r/w] h,w 00000000 00000000 001e6c h ptpc63 [r/w] h,w 00000000 00000000 D D 001e70 h pcn64 [r/w] b,h,w 00000000 000000 - 0 pcsr64 [w] h,w xxxxxxxx xxxxxxxx ppg64 001e74 h pdut64 [w] h,w xxxxxxxx xxxxxxxx ptmr64 [r] h,w 11111111 11111111 001e78 h pcn264 [r/w] b,h,w -- 000000 ----- 110 p sdr64 [r/w] h,w 00000000 00000000 001e7c h ptpc64 [r/w] h,w 00000000 00000000 D D 001e80 h pcn65 [r/w] b,h,w 00000000 000000 - 0 pcsr65 [w] h,w xxxxxxxx xxxxxxxx ppg65 001e84 h pdut65 [w] h,w xxxxxxxx xxxxxxxx ptmr65 [r] h,w 11111111 11111111 001e88 h pcn 265 [r/w] b,h,w -- 000000 ----- 110 psdr65 [r/w] h,w 00000000 00000000 001e8c h ptpc65 [r/w] h,w 00000000 00000000 D D 001e90 h pcn66 [r/w] b,h,w 00000000 000000 - 0 pcsr66 [w] h,w xxxxxxxx xxxxxxxx ppg66 001e94 h pdut66 [w] h,w xxxxxxxx xxxxxxxx ptmr66 [r] h,w 11111111 11111111 001e98 h pcn266 [r/w] b,h,w -- 000000 ----- 110 psdr66 [r/w] h,w 00000000 00000000 001e9c h ptpc66 [r/w] h,w 00000000 00000000 D D 001ea0 h pcn67 [r/w] b,h,w 00000000 000000 - 0 pcsr67 [w] h,w xxxxxxxx xxxxxxxx ppg67 001ea4 h pdut67 [w ] h,w xxxxxxxx xxxxxxxx ptmr67 [r] h,w 11111111 11111111 001ea8 h pcn267 [r/w] b,h,w -- 000000 ----- 110 psdr67 [r/w] h,w 00000000 00000000 001eac h ptpc67 [r/w] h,w 00000000 00000000 D D 001eb0 h pcn68 [r/w] b,h,w 00000000 000000 - 0 pcsr68 [w] h,w xxxxxxx x xxxxxxxx ppg68 001eb4 h pdut68 [w] h,w xxxxxxxx xxxxxxxx ptmr68 [r] h,w 11111111 11111111 001eb8 h pcn268 [r/w] b,h,w -- 000000 ----- 110 psdr68 [r/w] h,w 00000000 00000000 001ebc h ptpc68 [r/w] h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 125 confidential address address offset value / register name block +0 +1 +2 +3 001ec0 h pcn69 [r/w] b,h,w 00000 000 000000 - 0 pcsr69 [w] h,w xxxxxxxx xxxxxxxx ppg69 001ec4 h pdut69 [w] h,w xxxxxxxx xxxxxxxx ptmr69 [r] h,w 11111111 11111111 001ec8 h pcn269 [r/w] b,h,w -- 000000 ----- 110 psdr69 [r/w] h,w 00000000 00000000 001ecc h ptpc69 [r/w] h,w 00000000 00000000 D D 001ed0 h pcn70 [r/w] b,h,w 00000000 000000 - 0 pcsr70 [w] h,w xxxxxxxx xxxxxxxx ppg70 001ed4 h pdut70 [w] h,w xxxxxxxx xxxxxxxx ptmr70 [r] h,w 11111111 11111111 001ed8 h pcn270 [r/w] b,h,w -- 000000 ----- 110 psdr70 [r/w] h,w 00000000 00000000 001edc h pt pc70 [r/w] h,w 00000000 00000000 D D 001ee0 h pcn71 [r/w] b,h,w 00000000 000000 - 0 pcsr71 [w] h,w xxxxxxxx xxxxxxxx ppg71 001ee4 h pdut71 [w] h,w xxxxxxxx xxxxxxxx ptmr71 [r] h,w 11111111 11111111 001ee8 h pcn271 [r/w] b,h,w -- 000000 ----- 110 psdr71 [r/w] h,w 00000000 00000000 001eec h ptpc71 [r/w] h,w 00000000 00000000 D D 001ef0 h pcn72 [r/w] b,h,w 00000000 000000 - 0 pcsr72 [w] h,w xxxxxxxx xxxxxxxx ppg72 001ef4 h pdut72 [w] h,w xxxxxxxx xxxxxxxx ptmr72 [r] h,w 11111111 11111111 001ef8 h pcn272 [r/w] b ,h,w -- 000000 ----- 110 psdr72 [r/w] h,w 00000000 00000000 001efc h ptpc72 [r/w] h,w 00000000 00000000 D D 001f00 h pcn73 [r/w] b,h,w 00000000 000000 - 0 pcsr73 [w] h,w xxxxxxxx xxxxxxxx ppg73 001f04 h pdut73 [w] h,w xxxxxxxx xxxxxxxx ptmr73 [r] h,w 1111111 1 11111111 001f08 h pcn273 [r/w] b,h,w -- 000000 ----- 110 psdr73 [r/w] h,w 00000000 00000000 001f0c h ptpc73 [r/w] h,w 00000000 00000000 D D 001f10 h pcn74 [r/w] b,h,w 00000000 000000 - 0 pcsr74 [w] h,w xxxxxxxx xxxxxxxx ppg74 001f14 h pdut74 [w] h,w xxxxx xxx xxxxxxxx ptmr74 [r] h,w 11111111 11111111 001f18 h pcn274 [r/w] b,h,w -- 000000 ----- 110 psdr74 [r/w] h,w 00000000 00000000 001f1c h ptpc74 [r/w] h,w 00000000 00000000 D D d a t a s h e e t 126 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001f20 h pcn75 [r/w] b,h,w 00000000 000000 - 0 pcsr75 [w] h,w xxxxxxxx xxxxxxxx ppg75 001f24 h pdut75 [w] h,w xxxxxxxx xxxxxxxx ptmr75 [r] h,w 11111111 11111111 001f28 h pcn275 [r/w] b,h,w -- 000000 ----- 110 psdr75 [r/w] h,w 00000000 00000000 001f2c h ptpc75 [r/w] h,w 00000000 00000000 D D 001f30 h pcn76 [r/w] b,h,w 00000000 000000 - 0 pcsr76 [w] h,w xxxxxxxx xxxxxxxx ppg76 001f34 h pdut76 [w] h,w xxxxxxxx xxxxxxxx ptmr76 [r] h,w 11111111 11111111 001f38 h pcn276 [r/w] b,h,w -- 000000 ----- 110 psdr76 [r/w] h,w 00000000 00000000 001f3c h ptpc76 [r/w] h,w 00000000 00000000 D D 001f40 h pcn77 [r/w] b,h,w 00000000 000000 - 0 pcsr77 [w] h,w xxxxxxxx xxxxxxxx ppg77 001f44 h pdut77 [w] h,w xxxxxxxx xxxxxxxx ptmr77 [r] h,w 11111111 11111111 001f48 h pcn277 [r/w] b,h,w -- 000000 ----- 110 psdr77 [r/w] h,w 00000000 00000000 001f4c h ptpc77 [r/w] h,w 00000000 00000000 D D 001f50 h pcn78 [r/w] b,h,w 00000000 000000 - 0 pcsr78 [w] h,w xxxxxxxx xxxxxxxx ppg78 001f54 h pdut78 [w] h,w xxxxxxxx xxxxxxxx ptmr78 [r] h,w 11111111 11111111 001f58 h pcn278 [r/w] b,h,w -- 000000 ----- 110 psdr78 [r/w] h,w 000000 00 00000000 001f5c h ptpc78 [r/w] h,w 00000000 00000000 D D 001f60 h pcn79 [r/w] b,h,w 00000000 000000 - 0 pcsr79 [w] h,w xxxxxxxx xxxxxxxx ppg79 001f64 h pdut79 [w] h,w xxxxxxxx xxxxxxxx ptmr79 [r] h,w 11111111 11111111 001f68 h pcn279 [r/w] b,h,w -- 0000 00 ----- 110 psdr79 [r/w] h,w 00000000 00000000 001f6c h ptpc79 [r/w] h,w 00000000 00000000 D D 001f70 h pcn80 [r/w] b,h,w 00000000 000000 - 0 pcsr80 [w] h,w xxxxxxxx xxxxxxxx ppg80 001f74 h pdut80 [w] h,w xxxxxxxx xxxxxxxx ptmr80 [r] h,w 11111111 11111111 001f78 h pcn280 [r/w] b,h,w -- 000000 ----- 110 psdr80 [r/w] h,w 00000000 00000000 001f7c h ptpc80 [r/w] h,w 00000000 00000000 D D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 127 confidential address address offset value / register name block +0 +1 +2 +3 001f80 h pcn81 [r/w] b,h,w 00000000 000000 - 0 pcsr81 [w] h,w xxxxxxxx xxxxxxxx ppg81 001f84 h pdut81 [w] h,w xxxxxxxx xxxxxxx x ptmr81 [r] h,w 11111111 11111111 001f88 h pcn281 [r/w] b,h,w -- 000000 ----- 110 psdr81 [r/w] h,w 00000000 00000000 001f8c h ptpc81 [r/w] h,w 00000000 00000000 D D 001f90 h pcn82 [r/w] b,h,w 00000000 000000 - 0 pcsr82 [w] h,w xxxxxxxx xxxxxxxx ppg82 001f 94 h pdut82 [w] h,w xxxxxxxx xxxxxxxx ptmr82 [r] h,w 11111111 11111111 001f98 h pcn282 [r/w] b,h,w -- 000000 ----- 110 psdr82 [r/w] h,w 00000000 00000000 001f9c h ptpc82 [r/w] h,w 00000000 00000000 D D 001fa0 h pcn83 [r/w] b,h,w 00000000 000000 - 0 pcsr83 [w ] h,w xxxxxxxx xxxxxxxx ppg83 001fa4 h pdut83 [w] h,w xxxxxxxx xxxxxxxx ptmr83 [r] h,w 11111111 11111111 001fa8 h pcn283 [r/w] b,h,w -- 000000 ----- 110 psdr83 [r/w] h,w 00000000 00000000 001fac h ptpc83 [r/w] h,w 00000000 00000000 D D 001fb0 h pcn84 [r/w ] b,h,w 00000000 000000 - 0 pcsr84 [w] h,w xxxxxxxx xxxxxxxx ppg84 001fb4 h pdut84 [w] h,w xxxxxxxx xxxxxxxx ptmr84 [r] h,w 11111111 11111111 001fb8 h pcn284 [r/w] b,h,w -- 000000 ----- 110 psdr84 [r/w] h,w 00000000 00000000 001fbc h ptpc84 [r/w] h,w 0000000 0 00000000 D D 001fc0 h pcn85 [r/w] b,h,w 00000000 000000 - 0 pcsr85 [w] h,w xxxxxxxx xxxxxxxx ppg85 001fc4 h pdut85 [w] h,w xxxxxxxx xxxxxxxx ptmr85 [r] h,w 11111111 11111111 001fc8 h pcn285 [r/w] b,h,w -- 000000 ----- 110 psdr85 [r/w] h,w 00000000 00000000 001fcc h ptpc85 [r/w] h,w 00000000 00000000 D D 001fd0 h pcn86 [r/w] b,h,w 00000000 000000 - 0 pcsr86 [w] h,w xxxxxxxx xxxxxxxx ppg86 001fd4 h pdut86 [w] h,w xxxxxxxx xxxxxxxx ptmr86 [r] h,w 11111111 11111111 001fd8 h pcn286 [r/w] b,h,w -- 000000 ----- 110 psdr86 [r/w] h,w 00000000 00000000 001fdc h ptpc86 [r/w] h,w 00000000 00000000 D D d a t a s h e e t 128 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 001fe0 h pcn87 [r/w] b,h,w 00000000 000000 - 0 pcsr87 [w] h,w xxxxxxxx xxxxxxxx ppg87 001fe4 h pdut87 [w] h,w xxxxxxxx xxxxxxxx ptmr87 [r] h,w 11111111 11111111 001fe8 h p cn287 [r/w] b,h,w -- 000000 ----- 110 psdr87 [r/w] h,w 00000000 00000000 001fec h ptpc87 [r/w] h,w 00000000 00000000 D D 001ff0 h to 001ffc h D D D D reserved d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 129 confidential address address offset value / register name block +0 +1 +2 +3 002000 h ctrlr0 [r/w] b,h,w -------- 000 - 0001 statr0 [r/w] b,h,w -------- 00000000 can0 (128msb) 002004 h errcnt0 [r] b,h,w 00000000 00000000 btr0 [r/w] b,h,w - 0100011 00000001 002008 h intr0 [r] b,h,w 00000000 00000000 testr0 [r/w] b,h,w -------- x00000 -- 00200c h brper0 [r/w] b,h,w -------- ---- 0000 D D 002010 h if1creq0 [r/w] b,h,w 0 ------- 00000 001 if1cmsk0 [r/w] b,h,w -------- 00000000 002014 h if1msk20 [r/w] b,h,w 11 - 11111 11111111 if1msk10 [r/w] b,h,w 11111111 11111111 002018 h if1arb20 [r/w] b,h,w 00000000 00000000 if1arb10 [r/w] b,h,w 00000000 00000000 00201c h if1mctr0 [r/w] b,h,w 000000 00 0 --- 0000 D D 002020 h if1dta10 [r/w] b,h,w 00000000 00000000 if1dta20 [r/w] b,h,w 00000000 00000000 002024 h if1dtb10 [r/w] b,h,w 00000000 00000000 if1dtb20 [r/w] b,h,w 00000000 00000000 002028 h D D D D 00202c h D D D D 002030 h , 002034 h reserved (if1 data mirror) 002038 h D D D D 00203c h D D D D 002040 h if2creq0 [r/w] b,h,w 0 ------- 00000001 if2cmsk0 [r/w] b,h,w -------- 00000000 002044 h if2msk20 [r/w] b,h,w 11 - 11111 11111111 if2msk10 [r/w] b,h,w 11111111 11111111 002048 h if2arb20 [r/w] b ,h,w 00000000 00000000 if2arb10 [r/w] b,h,w 00000000 00000000 00204c h if2mctr0 [r/w] b,h,w 00000000 0 --- 0000 D D 002050 h if2dta10 [r/w] b,h,w 00000000 00000000 if2dta20 [r/w] b,h,w 00000000 00000000 002054 h if2dtb10 [r/w] b,h,w 00000000 00000000 if2d tb20 [r/w] b,h,w 00000000 00000000 002058 h D D D D 00205c h D D D D 002060 h , 002064 h reserved (if2 data mirror) 002068 h to 00207c h D d a t a s h e e t 130 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 002080 h treqr20 [r] b,h,w 00000000 00000000 treqr10 [r] b,h,w 00000000 00000000 can0 (128msb) 002084 h treqr40 [r] b,h,w 00000000 00000000 treqr30 [r] b,h,w 00000000 00000000 002088 h treqr60 [r] b,h,w 00000000 00000000 treqr50 [r] b,h,w 00000000 00000000 00208c h treqr80 [r] b,h,w 00000000 00000000 treqr70 [r] b,h,w 00000000 00000000 002090 h newdt20 [r] b,h,w 000 00000 00000000 newdt10 [r] b,h,w 00000000 00000000 002094 h newdt40 [r] b,h,w 00000000 00000000 newdt30 [r] b,h,w 00000000 00000000 002098 h newdt60 [r] b,h,w 00000000 00000000 newdt50 [r] b,h,w 00000000 00000000 00209c h newdt80 [r] b,h,w 00000000 0000 0000 newdt70 [r] b,h,w 00000000 00000000 0020a0 h intpnd20 [r] b,h,w 00000000 00000000 intpnd10 [r] b,h,w 00000000 00000000 0020a4 h intpnd40 [r] b,h,w 00000000 00000000 intpnd30 [r] b,h,w 00000000 00000000 0020a8 h intpnd60 [r] b,h,w 00000000 00000000 intpnd50 [r] b,h,w 00000000 00000000 0020ac h intpnd80 [r] b,h,w 00000000 00000000 intpnd70 [r] b,h,w 00000000 00000000 0020b0 h msgval20 [r] b,h,w 00000000 00000000 msgval10 [r] b,h,w 00000000 00000000 0020b4 h msgval40 [r] b,h,w 00000000 00000000 msgv al30 [r] b,h,w 00000000 00000000 0020b8 h msgval60 [r] b,h,w 00000000 00000000 msgval50 [r] b,h,w 00000000 00000000 0020bc h msgval80 [r] b,h,w 00000000 00000000 msgval70 [r] b,h,w 00000000 00000000 0020c0 h to 0020fc h D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 131 confidential address address offset value / register name block +0 +1 +2 +3 002100 h ctrlr1 [r/w] b,h,w --- ----- 000 - 0001 statr1 [r/w] b,h,w -------- 00000000 can1 (128msb) 002104 h errcnt1 [r] b,h,w 00000000 00000000 btr1 [r/w] b,h,w - 0100011 00000001 002108 h intr1 [r] b,h,w 00000000 00000000 testr1 [r/w] b,h,w -------- x00000 -- 00210c h brper1 [r/w] b,h,w -------- ---- 0000 D D 002110 h if1creq1 [r/w] b,h,w 0 ------- 00000001 if1cmsk1 [r/w] b,h,w -------- 00000000 002114 h if1msk21 [r/w] b,h,w 11 - 11111 11111111 if1msk11 [r/w] b,h,w 11111111 11111111 002118 h if1arb21 [r/w] b,h,w 00000000 00000000 if1arb11 [r/w] b,h,w 00000000 00000000 00211c h if1mctr1 [r/w] b,h,w 00000000 0 --- 0000 D D 002120 h if1dta11 [r/w] b,h,w 00000000 00000000 if1dta21 [r/w] b,h,w 00000000 00000000 002124 h if1dtb11 [r/w] b,h,w 00000000 00000000 if1dtb21 [r/w] b,h,w 00000000 000000 00 002128 h D D D D 00212c h D D D D 002130 h , 002134 h reserved (if1 data mirror) 002138 h D D D D 00213c h D D D D 002140 h if2creq1 [r/w] b,h,w 0 ------- 00000001 if2cmsk1 [r/w] b,h,w -------- 00000000 002144 h if2msk21 [r/w] b,h,w 11 - 11111 1111111 1 if2msk11 [r/w] b,h,w 11111111 11111111 002148 h if2arb21 [r/w] b,h,w 00000000 00000000 if2arb11 [r/w] b,h,w 00000000 00000000 00214c h if2mctr1 [r/w] b,h,w 00000000 0 --- 0000 D D 002150 h if2dta11 [r/w] b,h,w 00000000 00000000 if2dta21 [r/w] b,h,w 0000 0000 00000000 002154 h if2dtb11 [r/w] b,h,w 00000000 00000000 if2dtb21 [r/w] b,h,w 00000000 00000000 002158 h D D D D 00215c h D D D D 002160 h , 002164 h reserved (if2 data mirror) 002168 h to 00217c h D d a t a s h e e t 132 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 002180 h treqr21 [r] b,h,w 00000000 00000000 tre qr11 [r] b,h,w 00000000 00000000 can1 (128msb) 002184 h treqr41 [r] b,h,w 00000000 00000000 treqr31 [r] b,h,w 00000000 00000000 002188 h treqr61 [r] b,h,w 00000000 00000000 treqr51 [r] b,h,w 00000000 00000000 00218c h treqr81 [r] b,h,w 00000000 00000000 treqr71 [r] b,h,w 00000000 00000000 002190 h newdt21 [r] b,h,w 00000000 00000000 newdt11 [r] b,h,w 00000000 00000000 002194 h newdt41 [r] b,h,w 00000000 00000000 newdt31 [r] b,h,w 00000000 00000000 002198 h newdt61 [r] b,h,w 00000000 00000000 newdt51 [r ] b,h,w 00000000 00000000 00219c h newdt81 [r] b,h,w 00000000 00000000 newdt71 [r] b,h,w 00000000 00000000 0021a0 h intpnd21 [r] b,h,w 00000000 00000000 intpnd11 [r] b,h,w 00000000 00000000 0021a4 h intpnd41 [r] b,h,w 00000000 00000000 intpnd31 [r] b,h, w 00000000 00000000 0021a8 h intpnd61 [r] b,h,w 00000000 00000000 intpnd51 [r] b,h,w 00000000 00000000 0021ac h intpnd81 [r] b,h,w 00000000 00000000 intpnd71 [r] b,h,w 00000000 00000000 0021b0 h msgval21 [r] b,h,w 00000000 00000000 msgval11 [r] b,h,w 00 000000 00000000 0021b4 h msgval41 [r] b,h,w 00000000 00000000 msgval31 [r] b,h,w 00000000 00000000 0021b8 h msgval61 [r] b,h,w 00000000 00000000 msgval51 [r] b,h,w 00000000 00000000 0021bc h msgval81 [r] b,h,w 00000000 00000000 msgval71 [r] b,h,w 000000 00 00000000 0021c0 h to 0021fc h D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 133 confidential address address offset value / register name block +0 +1 +2 +3 002200 h ctrlr2 [r/w] b,h,w -------- 000 - 0001 statr2 [r/w] b,h,w -------- 00000000 can2 (128msb) 002204 h errcnt2 [r] b,h,w 00000000 00000000 btr2 [r/w] b,h,w - 0100011 00000001 002208 h intr2 [r] b,h,w 00000000 00000000 testr2 [r/w] b,h,w -------- x00000 -- 00220c h brper2 [r/w] b,h,w -------- ---- 0000 D 002210 h if1creq2 [r/w] b,h,w 0 ------- 00000001 if1cmsk2 [r/w] b,h,w -------- 00000000 002214 h if1msk22 [r/w] b,h,w 11 - 11111 11111111 if1msk12 [r/w] b,h,w 11111111 11 111111 002218 h if1arb22 [r/w] b,h,w 00000000 00000000 if1arb12 [r/w] b,h,w 00000000 00000000 00221c h if1mctr2 [r/w] b,h,w 00000000 0 --- 0000 D 002220 h if1dta12 [r/w] b,h,w 00000000 00000000 if1dta22 [r/w] b,h,w 00000000 00000000 002224 h if1dtb12 [r/ w] b,h,w 00000000 00000000 if1dtb22 [r/w] b,h,w 00000000 00000000 002228 h D D D D 00222c h D D D D 002230 h , 002234 h reserved (if1 data mirror) 002238 h D D D D 00223c h D D D D 002240 h if2creq2 [r/w] b,h,w 0 ------- 00000001 if2cmsk2 [r/w] b,h,w -- ------ 00000000 002244 h if2msk22 [r/w] b,h,w 11 - 11111 11111111 if2msk12 [r/w] b,h,w 11111111 11111111 002248 h if2arb22 [r/w] b,h,w 00000000 00000000 if2arb12 [r/w] b,h,w 00000000 00000000 00224c h if2mctr2 [r/w] b,h,w 00000000 0 --- 0000 D 002250 h if2 dta12 [r/w] b,h,w 00000000 00000000 if2dta22 [r/w] b,h,w 00000000 00000000 002254 h if2dtb12 [r/w] b,h,w 00000000 00000000 if2dtb22 [r/w] b,h,w 00000000 00000000 002258 h D D D D 00225c h D D D D 002260 h , 002264 h reserved (if2 data mirror) 002268 h t o 00227c h D d a t a s h e e t 134 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 002280 h treqr22 [r] b,h,w 00000000 00000000 treqr12 [r] b,h,w 00000000 00000000 can2 (128msb) 002284 h treqr42 [r] b,h,w 00000000 00000000 treqr32 [r] b,h,w 00000000 00000000 002288 h treqr62 [r] b,h,w 00000000 00000000 treqr52 [r] b,h,w 000 00000 00000000 00228c h treqr82 [r] b,h,w 00000000 00000000 treqr72 [r] b,h,w 00000000 00000000 002290 h newdt22 [r] b,h,w 00000000 00000000 newdt12 [r] b,h,w 00000000 00000000 002294 h newdt42 [r] b,h,w 00000000 00000000 newdt32 [r] b,h,w 00000000 0000 0000 002298 h newdt62 [r] b,h,w 00000000 00000000 newdt52 [r] b,h,w 00000000 00000000 00229c h newdt82 [r] b,h,w 00000000 00000000 newdt72 [r] b,h,w 00000000 00000000 0022a0 h intpnd22 [r] b,h,w 00000000 00000000 intpnd12 [r] b,h,w 00000000 00000000 0 022a4 h intpnd42 [r] b,h,w 00000000 00000000 intpnd32 [r] b,h,w 00000000 00000000 0022a8 h intpnd62 [r] b,h,w 00000000 00000000 intpnd52 [r] b,h,w 00000000 00000000 0022ac h intpnd82 [r] b,h,w 00000000 00000000 intpnd72 [r] b,h,w 00000000 00000000 0022b 0 h msgval22 [r] b,h,w 00000000 00000000 msgval12 [r] b,h,w 00000000 00000000 0022b4 h msgval42 [r] b,h,w 00000000 00000000 msgval32 [r] b,h,w 00000000 00000000 0022b8 h msgval62 [r] b,h,w 00000000 00000000 msgval52 [r] b,h,w 00000000 00000000 0022bc h m sgval82 [r] b,h,w 00000000 00000000 msgval72 [r] b,h,w 00000000 00000000 0022c0 h to 0022fc h D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 135 confidential address address offset value / register name block +0 +1 +2 +3 002300 h dfctlr [r/w] b,h,w - 0 ------ -------- D dfstr [r/w] b,h,w ----- 001 workflash 002304 h D D D D 002308 h flifctlr [r/w] b,h,w --- 0 -- 00 D fliffer1 [r/w] b,h,w -------- fliffer2 [r/w] b,h,w -------- flash / workflash 00230c h D reserved 002310 h trcr [r/w] b,h,w 00000000 trar [r/w] b,h,w 00000000 D tuningram 002314 h to 0023fc h D reserved 002400 h seearx [r] b,h,w 00000000 00000000 deearx [r] b,h,w 0000 0000 00000000 xbs ram ecc control 002404 h eecsrx [r/w] b,h,w ---- 00 -- D efearx [r/w] b,h,w 00000000 00000000 002408 h D efecrx [r/w] b,h,w ------- 0 00000000 00000000 00240c h to 002 4 fc h D reserved d a t a s h e e t 136 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 002500 h ctrlr3 [r/w] b,h,w -------- 000 - 0001 statr3 [r /w] b,h,w -------- 00000000 can3 (128msb) 002504 h errcnt3 [r] b,h,w 00000000 00000000 btr3 [r/w] b,h,w - 0100011 00000001 002508 h intr3 [r] b,h,w 00000000 00000000 testr3 [r/w] b,h,w -------- x00000 -- 00250c h brper3 [r/w] b,h,w -------- ---- 0000 D D 002510 h if1creq3 [r/w] b,h,w 0 ------- 00000001 if1cmsk3 [r/w] b,h,w -------- 00000000 002514 h if1msk23 [r/w] b,h,w 11 - 11111 11111111 if1msk13 [r/w] b,h,w 11111111 11111111 002518 h if1arb23 [r/w] b,h,w 00000000 00000000 if1arb13 [r/w] b,h,w 00000000 000 00000 00251c h if1mctr3 [r/w] b,h,w 00000000 0 --- 0000 D D 002520 h if1dta13 [r/w] b,h,w 00000000 00000000 if1dta23 [r/w] b,h,w 00000000 00000000 002524 h if1dtb13 [r/w] b,h,w 00000000 00000000 if1dtb23 [r/w] b,h,w 00000000 00000000 002528 h D D D D 0 0252c h D D D D 002530 h , 002534 h reserved (if1 data mirror) 002538 h D D D D 00253c h D D D D 002540 h if2creq3 [r/w] b,h,w 0 ------- 00000001 if2cmsk3 [r/w] b,h,w -------- 00000000 002544 h if2msk23 [r/w] b,h,w 11 - 11111 11111111 if2msk13 [r/w] b,h,w 1 1111111 11111111 002548 h if2arb23 [r/w] b,h,w 00000000 00000000 if2arb13 [r/w] b,h,w 00000000 00000000 00254c h if2mctr3 [r/w] b,h,w 00000000 0 --- 0000 D D 002550 h if2dta13 [r/w] b,h,w 00000000 00000000 if2dta23 [r/w] b,h,w 00000000 00000000 002554 h if2dtb13 [r/w] b,h,w 00000000 00000000 if2dtb23 [r/w] b,h,w 00000000 00000000 002558 h D D D D 00255c h D D D D 002560 h , 002564 h reserved (if2 data mirror) 002568 h D D D D 00256c h D D D D 002570 h to 00257c h D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 137 confidential address address offset value / register name block +0 +1 +2 +3 002580 h treqr23 [r] b,h,w 00000000 00000000 treqr13 [r] b,h,w 00000000 00000000 can3 (128msb) 002584 h treqr43 [r] b,h,w 00000000 00000000 treqr33 [r] b,h,w 00000000 00000000 002588 h treqr63 [r] b,h,w 00000000 00000000 treqr53 [r] b,h,w 00000000 00000000 00258c h treqr83 [r] b,h,w 000000 00 00000000 treqr73 [r] b,h,w 00000000 00000000 002590 h newdt23 [r] b,h,w 00000000 00000000 newdt13 [r] b,h,w 00000000 00000000 002594 h newdt43 [r] b,h,w 00000000 00000000 newdt33 [r] b,h,w 00000000 00000000 002598 h newdt63 [r] b,h,w 00000000 0000000 0 newdt53 [r] b,h,w 00000000 00000000 00259c h newdt83 [r] b,h,w 00000000 00000000 newdt73 [r] b,h,w 00000000 00000000 0025a0 h intpnd23 [r] b,h,w 00000000 00000000 intpnd13 [r] b,h,w 00000000 00000000 0025a4 h intpnd43 [r] b,h,w 00000000 00000000 intpn d33 [r] b,h,w 00000000 00000000 0025a8 h intpnd63 [r] b,h,w 00000000 00000000 intpnd53 [r] b,h,w 00000000 00000000 0025ac h intpnd83 [r] b,h,w 00000000 00000000 intpnd73 [r] b,h,w 00000000 00000000 0025b0 h msgval23 [r] b,h,w 00000000 00000000 msgval13 [r] b,h,w 00000000 00000000 0025b4 h msgval43 [r] b,h,w 00000000 00000000 msgval33 [r] b,h,w 00000000 00000000 0025b8 h msgval63 [r] b,h,w 00000000 00000000 msgval53 [r] b,h,w 00000000 00000000 0025bc h msgval83 [r] b,h,w 00000000 00000000 msgval73 [r] b,h,w 00000000 00000000 0025c0 h to 0025fc h D d a t a s h e e t 138 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 002600 h ctrlr4 [r/w] b,h,w -------- 000 - 0001 statr4 [r/w] b,h,w -------- 00000000 can4 (128msb) 002604 h errcnt4 [r] b,h,w 00000000 00000000 btr4 [r/w] b,h,w - 0100011 00000001 002608 h intr4 [r] b,h,w 00000 000 00000000 testr4 [r/w] b,h,w -------- x00000 -- 00260c h brper4 [r/w] b,h,w -------- ---- 0000 D D 002610 h if1creq4 [r/w] b,h,w 0 ------- 00000001 if1cmsk4 [r/w] b,h,w -------- 00000000 002614 h if1msk24 [r/w] b,h,w 11 - 11111 11111111 if1msk14 [r/w] b,h ,w 11111111 11111111 002618 h if1arb24 [r/w] b,h,w 00000000 00000000 if1arb14 [r/w] b,h,w 00000000 00000000 00261c h if1mctr4 [r/w] b,h,w 00000000 0 --- 0000 D D 002620 h if1dta14 [r/w] b,h,w 00000000 00000000 if1dta24 [r/w] b,h,w 00000000 00000000 0026 24 h if1dtb14 [r/w] b,h,w 00000000 00000000 if1dtb24 [r/w] b,h,w 00000000 00000000 002628 h D D D D 00262c h D D D D 002630 h , 002634 h reserved (if1 data mirror) 002638 h D D D D 00263c h D D D D 002640 h if2creq4 [r/w] b,h,w 0 ------- 00000001 if2cmsk 4 [r/w] b,h,w -------- 00000000 002644 h if2msk24 [r/w] b,h,w 11 - 11111 11111111 if2msk14 [r/w] b,h,w 11111111 11111111 002648 h if2arb24 [r/w] b,h,w 00000000 00000000 if2arb14 [r/w] b,h,w 00000000 00000000 00264c h if2mctr4 [r/w] b,h,w 00000000 0 --- 0000 D D 002650 h if2dta14 [r/w] b,h,w 00000000 00000000 if2dta24 [r/w] b,h,w 00000000 00000000 002654 h if2dtb14 [r/w] b,h,w 00000000 00000000 if2dtb24 [r/w] b,h,w 00000000 00000000 002658 h D D D D 00265c h D D D D 002660 h , 002664 h reserved (if2 data m irror) 002668 h D D D D 00266c h D D D D 002670 h to 00267c h D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 139 confidential address address offset value / register name block +0 +1 +2 +3 002680 h treqr24 [r] b,h,w 00000000 00000000 treqr14 [r] b,h,w 00000000 00000000 can4 (128msb) 002684 h treqr44 [r] b,h,w 00000000 00000000 treqr34 [r] b,h,w 00000000 00000000 002688 h tre qr64 [r] b,h,w 00000000 00000000 treqr54 [r] b,h,w 00000000 00000000 00268c h treqr84 [r] b,h,w 00000000 00000000 treqr74 [r] b,h,w 00000000 00000000 002690 h newdt24 [r] b,h,w 00000000 00000000 newdt14 [r] b,h,w 00000000 00000000 002694 h newdt44 [r] b ,h,w 00000000 00000000 newdt34 [r] b,h,w 00000000 00000000 002698 h newdt64 [r] b,h,w 00000000 00000000 newdt54 [r] b,h,w 00000000 00000000 00269c h newdt84 [r] b,h,w 00000000 00000000 newdt74 [r] b,h,w 00000000 00000000 0026a0 h intpnd24 [r] b,h,w 0000 0000 00000000 intpnd14 [r] b,h,w 00000000 00000000 0026a4 h intpnd44 [r] b,h,w 00000000 00000000 intpnd34 [r] b,h,w 00000000 00000000 0026a8 h intpnd64 [r] b,h,w 00000000 00000000 intpnd54 [r] b,h,w 00000000 00000000 0026ac h intpnd84 [r] b,h,w 00000000 00000000 intpnd74 [r] b,h,w 00000000 00000000 0026b0 h msgval24 [r] b,h,w 00000000 00000000 msgval14 [r] b,h,w 00000000 00000000 0026b4 h msgval44 [r] b,h,w 00000000 00000000 msgval34 [r] b,h,w 00000000 00000000 0026b8 h msgval64 [r] b,h,w 00000000 000 00000 msgval54 [r] b,h,w 00000000 00000000 0026bc h msgval84 [r] b,h,w 00000000 00000000 msgval74 [r] b,h,w 00000000 00000000 0026c0 h to 0026fc h D d a t a s h e e t 140 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 002700 h ctrlr5 [r/w] b,h,w -------- 000 - 0001 statr5 [r/w] b,h,w -------- 00000000 can5 (128msb) 002704 h errcnt5 [r] b,h,w 00000000 00000000 btr5 [r/w] b,h,w - 0100011 00000001 002708 h intr5 [r] b,h,w 00000000 00000000 testr5 [r/w] b,h,w -------- x00000 -- 00270c h brper5 [r/w] b,h,w -------- ---- 0000 D D 002710 h if1creq5 [r/w] b,h,w 0 ------- 00000001 if1 cmsk5 [r/w] b,h,w -------- 00000000 002714 h if1msk25 [r/w] b,h,w 11 - 11111 11111111 if1msk15 [r/w] b,h,w 11111111 11111111 002718 h if1arb25 [r/w] b,h,w 00000000 00000000 if1arb15 [r/w] b,h,w 00000000 00000000 00271c h if1mctr5 [r/w] b,h,w 00000000 0 --- 0000 D D 002720 h if1dta15 [r/w] b,h,w 00000000 00000000 if1dta25 [r/w] b,h,w 00000000 00000000 002724 h if1dtb15 [r/w] b,h,w 00000000 00000000 if1dtb25 [r/w] b,h,w 00000000 00000000 002728 h D D D D 00272c h D D D D 002730 h , 002734 h reserved (if1 da ta mirror) 002738 h D D D D 00273c h D D D D 002740 h if2creq5 [r/w] b,h,w 0 ------- 00000001 if2cmsk5 [r/w] b,h,w -------- 00000000 002744 h if2msk25 [r/w] b,h,w 11 - 11111 11111111 if2msk15 [r/w] b,h,w 11111111 11111111 002748 h if2arb25 [r/w] b,h,w 00 000000 00000000 if2arb15 [r/w] b,h,w 00000000 00000000 00274c h if2mctr5 [r/w] b,h,w 00000000 0 --- 0000 D D 002750 h if2dta15 [r/w] b,h,w 00000000 00000000 if2dta25 [r/w] b,h,w 00000000 00000000 002754 h if2dtb15 [r/w] b,h,w 00000000 00000000 if2dtb25 [r /w] b,h,w 00000000 00000000 002758 h D D D D 00275c h D D D D 002760 h , 002764 h reserved (if2 data mirror) 002768 h D D D D 00276c h D D D D 002770 h to 00277c h D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 141 confidential address address offset value / register name block +0 +1 +2 +3 002780 h treqr25 [r] b,h,w 00000000 00000000 treqr15 [r] b,h,w 00000000 00000000 can5 (128msb) 002784 h treqr45 [r] b,h,w 00000000 00000000 treqr35 [r] b,h,w 00000000 00000000 002788 h treqr65 [r] b,h,w 00000000 00000000 treqr55 [r] b,h,w 00000000 00000000 00278c h treqr85 [r] b,h,w 00000000 00000000 treqr75 [r] b,h,w 00000000 00000000 002790 h newdt25 [r] b,h,w 00000000 00000000 newdt15 [r] b,h,w 00000000 00000000 002794 h newdt45 [r] b,h,w 00000000 00000000 newdt35 [r] b,h,w 00000000 00000000 002798 h newdt65 [r] b,h,w 00000000 00000000 newdt55 [r] b,h,w 00000000 00000000 00279c h ne wdt85 [r] b,h,w 00000000 00000000 newdt75 [r] b,h,w 00000000 00000000 0027a0 h intpnd25 [r] b,h,w 00000000 00000000 intpnd15 [r] b,h,w 00000000 00000000 0027a4 h intpnd45 [r] b,h,w 00000000 00000000 intpnd35 [r] b,h,w 00000000 00000000 0027a8 h intpnd65 [r] b,h,w 00000000 00000000 intpnd55 [r] b,h,w 00000000 00000000 0027ac h intpnd85 [r] b,h,w 00000000 00000000 intpnd75 [r] b,h,w 00000000 00000000 0027b0 h msgval25 [r] b,h,w 00000000 00000000 msgval15 [r] b,h,w 00000000 00000000 0027b4 h msgval45 [r] b,h,w 00000000 00000000 msgval35 [r] b,h,w 00000000 00000000 0027b8 h msgval65 [r] b,h,w 00000000 00000000 msgval55 [r] b,h,w 00000000 00000000 0027bc h msgval85 [r] b,h,w 00000000 00000000 msgval75 [r] b,h,w 00000000 00000000 0027c0 h to 002ffc h D d a t a s h e e t 142 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 0 03000 h seeara [r] b,h,w ---- 0000 00000000 deeara [r] b,h,w ---- 0000 00000000 backup ram ecc control 003004 h eecsra [r/w] b,h,w ---- 00 -- D efeara [r/w] b,h,w ---- 0000 00000000 003008 h D efecra [r/w] b,h,w ------- 0 00000000 00000000 00300c h tear0x[r] b ,h,w 000 ----- -------- 00000000 00000000 ram/diagnosis xbs ram 003010 h tear1x[r] b,h,w 000 ----- -------- 00000000 00000000 003014 h tear2x[r] b,h,w 000 ----- -------- 00000000 00000000 003018 h taearx [r/w] b,h,w 10111111 11111111 tasarx [r/w] b,h,w 0000 0000 00000000 00301c h tfecrx [r/w] b,h,w ---- 0000 ticrx [r/w] b,h,w ---- 0000 ttcrx [r/w] b,h,w ------ 00 00001100 003020 h tsrcrx [w] b,h,w 0 ------- D D tkccrx [r/w] b,h,w 00 ---- 00 003024 h to 00302c h D reserved 003030 h tear0a[r] b,h,w 000 ----- --- ----- ---- 0000 00000000 ram/diagnosis backup ram 003034 h tear1a[r] b,h,w 000 ----- -------- ---- 0000 00000000 003038 h tear2a[r] b,h,w 000 ----- -------- ---- 0000 00000000 00303c h taeara[r/w] b,h,w ---- 1111 11111111 tasara[r/w] b,h,w ---- 0000 00000000 003040 h tfecra [r/w] b,h,w ---- 0000 ticra [r/w] b,h,w ---- 0000 ttcra [r/w] b,h,w ------ 00 00001100 003044 h tsrcra [w] b,h,w 0 ------- D D tkccra [r/w] b,h,w 00 ---- 00 003048 h , 00304c h D reserved d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 143 confidential address address offset value / register name block +0 +1 +2 +3 003050 h seearh [r] b,h,w -- 000000 00000000 deearh [r] b,h,w -- 000000 00000000 ahb ram ecc control 003054 h eecsrh [r/w] b,h,w ---- 00 -- D efearh [r/w] b,h,w -- 000000 00000000 003058 h D efecrh [r/w] b,h,w ------- 0 00000000 00000000 00305c h D reserved 003060 h tear0h[r] b,h,w 000 ----- -------- -- 000000 000 00000 ram/diagnosis ahb ram 003064 h tear1h[r] b,h,w 000 ----- -------- -- 000000 00000000 003068 h tear2h[r] b,h,w 000 ----- -------- -- 000000 00000000 00306c h taearh[r/w] b,h,w -- 111111 11111111 tasarh[r/w] b,h,w -- 000000 00000000 003070 h tfecrh [r/w] b,h,w ---- 0000 ticrh [r/w] b,h,w ---- 0000 ttcrh [r/w] b,h,w ------ 00 00001100 003074 h tsrcrh [w] b,h,w 0 ------- D D tkccrh [r/w] b,h,w 00 ---- 00 003078 h to 0030fc h D reserved 003100 h busdigsr0[r/w] h,w 00000000 0 ----- 00 busdigsr1[r/w] h,w 00000000 0 ----- 00 bus diagnosis 003104 h busdigsr2[r/w] h,w 00000000 0 ----- 00 buststr0[r/w] h,w 00 -- 0000 00000000 003108 h busadr0 [r] w 00000000 00000000 00000000 00000000 00310c h busadr1 [r] w 00000000 00000000 00000000 00000000 003110 h busadr2 [r] w 0000000 0 00000000 00000000 00000000 003114 h D D busdigsr3[r/w] h,w 00000000 0 ----- 00 003118 h busdigsr4[r/w] h,w 00000000 0 ----- 00 buststr1[r/w] h,w 00 -- 000 - 00000000 00311c h D D D D 003120 h busadr3 [r] w 00000000 00000000 00000000 00000000 003124 h busad r4 [r] w 00000000 00000000 00000000 00000000 003128 h to 003ffc h D reserved 004000 h to 007ffc h backup - ram backup ram area 008000 h to 00cffc h D D D D reserved d a t a s h e e t 144 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 00d000 h cif0[r] w 00000100 11111111 01011011 11111111 flexray cif 00d004 h cif1[r/w] w 0000000 0 ------- 0 - 0000000 -------- 00d008 h to 00d018 h D D D D reserved 00d01c h lck[r/w] w -------- -------- -------- 00000000 flexray gif 00d020 h eir[r/w] w ----- 000 ----- 000 ---- 0000 00000000 flexray int 00d024 h sir[r/w] w ------ 00 ------ 00 00000000 000000 00 00d028 h eils[r/w] w ----- 000 ----- 000 ---- 0000 00000000 00d02c h sils[r/w] w ------ 11 ------ 11 11111111 11111111 00d030 h eies[r/w] w ----- 000 ----- 000 ---- 0000 00000000 00d034 h eier[r/w] w ----- 000 ----- 000 ---- 0000 00000000 00d038 h sies[r/w] w ------ 00 ------ 00 00000000 00000000 00d03c h sier[r/w] w ------ 00 ------ 00 00000000 00000000 00d040 h ile[r/w] w -------- -------- -------- ------ 00 00d044 h t0c[r/w] w -- 000000 00000000 - 0000000 ------ 00 00d048 h t1c[r/w] w -- 000000 00000010 -------- ------ 00 00d04c h stpw1[r/w] w -- 000000 00000000 -- 000000 - 0000000 00d050 h stpw2[r] w ----- 000 00000000 ----- 000 00000000 00d054 h to 00d07c h D D D D reserved 00d080 h succ1[r/w] w ---- 1100 01000000 00010 - 00 1 --- 0000 flexray suc 00d084 h succ2[r/w] w ---- 0001 --- 00000 00000101 00000100 00d088 h succ3[r/w] w -------- -------- -------- 00010001 00d08c h nemc[r/w] w -------- -------- -------- ---- 0000 flexray nem 00d090 h prtc1[r/w] w 000010 - 0 01001100 0000 - 110 00110011 flexray prt 00d094 h prtc2[r/w] w -- 001111 00101101 -- 001010 - C 001110 00d098 h mhdc[r/w] w --- 00000 00000000 -------- - 0000000 flexray mhd 00d09c h D reserved d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 145 confidential address address offset value / register name block +0 +1 +2 +3 00d0a0 h gtuc1[r/w] w -------- ---- 0000 00000010 10000000 flexray gtu 00d0a4 h gtuc2[r/w] w -------- ---- 0010 -- 000000 00001010 00d0a8 h gtuc3[r/w] w - 0000010 - 0000010 00000000 00000000 00d0ac h gtuc4[r/w] w -- 000000 00001000 -- 000000 00000111 00d0b0 h gtuc5[r/w] w 00001110 --- 00000 00000000 00000000 00d0b4 h gtuc6[r/w] w ----- 000 00000010 ----- 000 00000000 00d0b8 h gtuc7[r/w] w ------ 00 00000010 ------ 00 00000100 00d0bc h gtuc8[r/w] w --- 00000 00000000 -------- -- 000010 00d0c0 h gtuc9[r/w] w -------- ------ 00 --- 00001 - C 000001 00d0c4 h gtuc10[r/w] w ----- 000 00000010 -- 000000 00000101 00d0c8 h gtuc11[r/w] w ----- 000 ----- 00 0 ------ 00 ------ 00 00d0cc h to 00d0fc h D D D D reserved 00d100 h ccsv[r] w -- 000000 00010000 - 100 -- 00 00000000 flexray suc 00d104 h ccev[r] w -------- -------- --- 00000 00 -- 0000 00d108 h D reserved 00d10c h D 00d110 h scv[r] w ----- 000 00000000 ----- 00 0 00000000 flexray gtu 00d114 h mtccv[r] w -------- -- 000000 -- 000000 00000000 00d118 h rcv[r] w -------- -------- ---- 0000 00000000 00d11c h ocv[r] w -------- ----- 000 00000000 00000000 00d120 h sfs[r] w -------- ---- 0000 00000000 00000000 00d124 h sw nit[r] w -------- -------- ---- 0000 00000000 00d128 h acs[r/w] w -------- -------- --- 00000 --- 00000 00d12c h D d a t a s h e e t 146 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 00d130 h esid1[r] w -------- -------- 00 ---- 00 00000000 flexray gtu 00d134 h esid2[r] w -------- -------- 00 ---- 00 00000000 00d138 h esid3[r ] w -------- -------- 00 ---- 00 00000000 00d13c h esid4[r] w -------- -------- 00 ---- 00 00000000 00d140 h esid5[r] w -------- -------- 00 ---- 00 00000000 00d144 h esid6[r] w -------- -------- 00 ---- 00 00000000 00d148 h esid7[r] w -------- -------- 00 ---- 00 00000000 00d14c h esid8[r] w -------- -------- 00 ---- 00 00000000 00d150 h esid9[r] w -------- -------- 00 ---- 00 00000000 00d154 h esid10[r] w -------- -------- 00 ---- 00 00000000 00d158 h esid11[r] w -------- -------- 00 ---- 00 00000000 00d15c h esid 12[r] w -------- -------- 00 ---- 00 00000000 00d160 h esid13[r] w -------- -------- 00 ---- 00 00000000 00d164 h esid14[r] w -------- -------- 00 ---- 00 00000000 00d168 h esid15[r] w -------- -------- 00 ---- 00 00000000 00d16c h D d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 147 confidential address address offset value / register name block +0 +1 +2 +3 00d170 h osid1[r] w ----- --- -------- 00 ---- 00 00000000 flexray gtu 00d174 h osid2[r] w -------- -------- 00 ---- 00 00000000 00d178 h osid3[r] w -------- -------- 00 ---- 00 00000000 00d17c h osid4[r] w -------- -------- 00 ---- 00 00000000 00d180 h osid5[r] w -------- -------- 00 -- -- 00 00000000 00d184 h osid6[r] w -------- -------- 00 ---- 00 00000000 00d188 h osid7[r] w -------- -------- 00 ---- 00 00000000 00d18c h osid8[r] w -------- -------- 00 ---- 00 00000000 00d190 h osid9[r] w -------- -------- 00 ---- 00 00000000 00d194 h osid 10[r] w -------- -------- 00 ---- 00 00000000 00d198 h osid11[r] w -------- -------- 00 ---- 00 00000000 00d19c h osid12[r] w -------- -------- 00 ---- 00 00000000 00d1a0 h osid13[r] w -------- -------- 00 ---- 00 00000000 00d1a4 h osid14[r] w -------- ------- - 00 ---- 00 00000000 00d1a8 h osid15[r] w -------- -------- 00 ---- 00 00000000 00d1ac h D reserved 00d1b0 h nmv1[r] w 00000000 00000000 00000000 00000000 flexray nem 00d1b4 h nmv2[r] w 00000000 00000000 00000000 00000000 00d1b8 h nmv3[r] w 00000000 000000 00 00000000 00000000 00d1bc h to 00d2fc h D D D D reserved d a t a s h e e t 148 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 00d300 h mrc[r/w] w ----- 001 10000000 00000000 00000000 flexray mhd 00d304 h frf[r/w] w ------- 1 10000000 --- 00000 00000000 00d308 h frfm[r/w] w -------- -------- --- 00000 000000 -- 00d30c h fcl[r /w] w -------- -------- -------- 10000000 00d310 h mhds[r/w] w - 0000000 - 0000000 - 0000000 10000000 00d314 h ldts[r] w ----- 000 00000000 ----- 000 00000000 00d318 h fsr[r] w -------- -------- 00000000 ----- 000 00d31c h mhdf[r/w] w -------- -------- ----- -- 0 00000000 00d320 h txrq1[r] w 00000000 00000000 00000000 00000000 00d324 h txrq2[r] w 00000000 00000000 00000000 00000000 00d328 h txrq3[r] w 00000000 00000000 00000000 00000000 00d32c h txrq4[r] w 00000000 00000000 00000000 00000000 00d330 h ndat1 [r] w 00000000 00000000 00000000 00000000 00d334 h ndat2[r] w 00000000 00000000 00000000 00000000 00d338 h ndat3[r] w 00000000 00000000 00000000 00000000 00d33c h ndat4[r] w 00000000 00000000 00000000 00000000 00d340 h mbsc1[r] w 00000000 00000000 0000 0000 00000000 00d344 h mbsc2[r] w 00000000 00000000 00000000 00000000 00d348 h mbsc3[r] w 00000000 00000000 00000000 00000000 00d34c h mbsc4[r] w 00000000 00000000 00000000 00000000 00d350 h to 00d3ec h D D D D reserved 00d3f0 h crel[r] w 00010000 00111 001 00000010 00000110 flexray gif 00d3f4 h endn[r] w 10000111 01100101 01000011 00100001 00d3f8 h , 00d3fc h D D D D reserved d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 149 confidential address address offset value / register name block +0 +1 +2 +3 00d400 h to 00d4fc h wrdsn[1 - 64][r/w] w 00000000 00000000 00000000 00000000 flexray ibf 00d500 h wrhs1[r/w] w -- 000000 - 0000000 ---- - 000 00000000 00d504 h wrhs2[r/w] w -------- - 0000000 ----- 000 00000000 00d508 h wrhs3[r/w] w -------- -------- ----- 000 00000000 00d50c h D 00d510 h ibcm[r/w] w -------- ----- 000 -------- ----- 000 00d514 h ibcr[r/w] w 0 ------- - 0000000 0 ------- - 0000 000 00d518 h to 00d5fc h D D D D reserved 00d600 h to 00d6fc h rddsn[1 - 64][r] w 00000000 00000000 00000000 00000000 flexray obf 00d700 h rdhs1[r] w -- 000000 - 0000000 ----- 000 00000000 00d704 h rdhs2[r] w - 0000000 - 0000000 ----- 000 00000000 00d708 h rdhs3[ r] w -- 000000 -- 000000 ----- 000 00000000 00d70c h mbs[r] w -- 000000 -- 000000 00 - 00000 00000000 00d710 h obcm[r/w] w -------- ------ 00 -------- ------ 00 00d714 h obcr[r/w] w -------- - 0000000 0 ----- 00 - 0000000 00d718 h to 00d7fc h D D D D reserved 00d80 0 h to 00effc h D D D D reserved d a t a s h e e t 150 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confid ential address address offset value / register name block +0 +1 +2 +3 00f000 h to 00fefc h D D D D reserved [s] 00ff00 h dsucr [r/w] b,h,w -------- ------- 0 D D ocdu [s] 00ff04 h to 00ff0c h D reserved [s] 00ff10 h pcsr [r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00ff14 h pssr [r/w] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00ff18 h to 00fff4 h D reserved [s] 00fff8 h edir1 [r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ocdu [s] 00fffc h edir0 [r] b,h,w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx [s]:it is a system register. the il legal instruction exception (data access error) is generated in these registers in the user mode when reading and writing to it. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 151 confidential ? interrupt vector table this list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers. ? interrupt vector ? mb91f52xr (144 pin ) interrupt factor interrupt number interrupt level offset default address for tbr rn * decim al hexa - decimal reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - except ion of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0 a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of illegal instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15(f h ) fixed 3c0 h 000fffc0 h - error generation at internal bus diagnosis xbs ram double - bit error detection backup ram double - bit error detection ahb ram double - bit error detection tpu violation external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 ext ernal interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1* 8 external low - voltage detection interrupt - reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2* 2 reload timer 2/3/6/7 19 13 icr03 3b0 h 000fffb0 h 3* 2 multi - function serial interface ch.0 (re ception completed) 20 14 icr04 3ac h 000fffac h 4* 1 multi - function serial interface ch.0 (status) multi - function serial interface ch.0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5* 1 multi - function serial interface ch.1 (reception completed) 22 16 icr06 3a4 h 000fffa4 h 6* 1 multi - function serial interface ch.1 (status) multi - function serial interface ch.1 (transmission completed) 23 17 icr07 3a0 h 000fffa0 h 7* 1 d a t a s h e e t 152 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decim al hexa - decimal multi - function serial interface ch.2 (reception completed) 24 18 icr08 39c h 000fff9c h 8* 1 multi - function serial interface ch.2 (status) multi - function serial interface ch.2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9* 1 multi - function serial interface ch.3 (reception completed) 26 1a icr10 394 h 000fff94 h 10* 1 mu lti - function serial interface ch.3 (status) multi - function serial interface ch.3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 multi - function serial interface ch.4 (reception completed) 28 1c icr12 38c h 000fff8c h 12* 1 multi - function seria l interface ch.4 (status) multi - function serial interface ch.4 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial interface ch.5 (reception completed) 30 1e icr14 384 h 000fff84 h 14* 1 multi - function serial interface ch.5 ( status) multi - function serial interface ch.5 (transmission completed) 31 1f icr15 380 h 000fff80 h 15* 9 flexray0 multi - function serial interface ch.6 (reception completed) 32 20 icr16 37c h 000fff7c h 16* 1 multi - function serial interface ch.6 ( status) flexray 1 multi - function serial interface ch.6 (transmission completed) 33 21 icr17 378 h 000fff78 h 17* 10 flexray timer 0 can0 34 22 icr18 374 h 000fff74 h - can3 flexray timer 1 can1 35 23 icr19 370 h 000fff70 h - r am diagnosis completed ram initialization completed e rror generation at ram diagnosis backup ram diagnosis completed backup ram initialization completed e rror generation at backup ram diagnosis ahb ram diagnosis co mpleted ahb ram initialization completed error generation at ahb ram diagnosis can 4 can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 up/down counter 1 can5 flexray pll gear/flexray pll alarm d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 153 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decim al hexa - decimal real time clock 37 25 icr21 368 h 000fff68 h - multi - function serial interface ch.7 (reception completed) 38 26 icr22 364 h 000fff64 h 22* 1 multi - function serial interface ch.7 (status) 16 - bit free - run timer 0 ( " 0 " detection) / (compare clear) 39 27 icr23 360 h 000fff60 h 23 multi - function serial interface ch.7 (transmission completed) ppg0/1/10/11/20/21/30/31/40/41 40 28 icr24 35c h 000fff5c h 24* 3 16 - bit free - run timer 1 ( " 0 " detection) / (compare clear) ppg2/3/12/13/22/23/32/33/43 41 29 icr25 358 h 000fff58 h 25* 3 16 - bit free - run timer 2 ( " 0 " detection) / (compare clear) ppg4/5/14/15/24/25/34/35/44 42 2a icr26 354 h 000fff54 h 26* 3 ppg6/7/16/17/26/27/36/37 43 2b icr27 350 h 000fff50 h 27* 3 ppg8/9/18/19/28/29 44 2c icr28 34c h 000fff4c h 28* 3 multi - function serial interface ch.8 (reception completed) 45 2d icr29 348 h 000fff48 h 29* 1 multi - fu nction serial interface ch.8 (status) 16 - bit icu 0 (fetching) / 16 - bit icu 1 (fetching) main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer multi - function serial interface ch.8 (transmission completed) 16 - bit icu 2 (fetching) /16 - bit icu 3 (fetching) clock calibration unit (sub oscillation) 47 2f icr31 340 h 000fff40 h 31* 1 * 4 multi - function serial interfac e ch.9 (reception completed) multi - function serial interface ch.9 (status) a/d converter 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16 17/18/19/20/21/22/23/24/25/26/27/28/29/30/31 48 30 icr32 33c h 000fff3c h 32 clock calibration unit (cr oscillat ion) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch.9 (transmission completed) 16 - bit ocu 0 (match) / 16 - bit ocu 1 (match) 32 - bit free - run timer 4 50 32 icr34 334 h 000fff34 h 34* 6 16 - bit ocu 2 (match) / 16 - bit ocu 3 (match) 32 - bit free - run timer 3/5 51 33 icr35 330 h 000fff30 h 35* 6 16 - bit ocu 4 (match) / 16 - bit ocu 5 (match) 32 - bit icu6 (fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36* 1 multi - function serial interface ch.10 (reception completed) mu lti - function serial interface ch.10 (status) 32 - bit icu7 (fetching / measurement ) 53 35 icr37 328 h 000fff28 h 37 multi - function serial interface ch.10 (transmission completed) d a t a s h e e t 154 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decim al hexa - decimal 32 - bit icu8 (fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38* 1 multi - function serial interface ch.11 (reception completed) multi - function serial interface ch.11 (status) 32 - bit icu9 (fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg dead timer underflow 0 / 1/ 2 wg dead timer reload 0 / 1 / 2 wg dtti 0 32 - bit icu4 (fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch.11 (transmission completed) 32 - bit icu5 (fetching / measurement ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/ 35/36/37/38/39/40/41/42/43/44/45/46/47 32 - bit ocu6/7/10/11 (match) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu8/9 (match) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 60 3c icr44 30c h 000fff0c h 44 base timer 0 irq1 base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45* 5 base timer 1 irq1 - - dmac0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delayed interrupt 63 3f icr47 300 h 000fff00 h - system reserved (used for realos tm * 11 ) 64 40 - 2fc h 000ffefc h - s ystem reserved (used for realos) 65 41 - 2f8 h 000ffef8 h - used with the int instruction. 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - *: it does not support the dma transfer request by the interrupt generated from a peripheral to which no rn (r esource number) is assigned. * 1: the status of the multi - function serial interface does not support the dma transfer by the i 2 c reception and flexray . * 2: the reload timer ch.4 to ch.7 does not support the dma transfer by the interrupt. * 3: the ppg ch.2 4 to ch. 8 7 does not support the dma transfer by the interrupt. * 4: the clock calibration unit does not support the dma transfer by the interrupt. * 5: it does not support the dma transfer by the interrupt because of the ram ecc bit error. * 6: the 32 - bit free - run timer ch.3 to ch. 10 does not support the dma transfer by the interrupt. * 8: it does not support the dma transfer by the external low - voltage detection interrupt. *9: it does not support the dma transfer by the flexray interrupt. *10: it does no t support the dma transfer by the flexray timer interrupt. *11: realos is a trademark of spansion llc. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 155 confidential ? mb91f52xu (176 pin ) interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal reset 0 0 - 3f c h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserve d 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of illegal instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15(f h ) fixed 3c0 h 000fffc0 h - error generation at internal bus dia gnosis xbs ram double - bit error detection backup ram double - bit error detection ahb ram double - bit error detection tpu violation external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1* 8 external low - voltage detection interrupt - reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2* 2 reload timer 2/3/6/7 19 13 icr03 3b0 h 000fffb0 h 3* 2 multi - function serial interface ch.0 (reception completed) 20 14 icr04 3ac h 000fffac h 4* 1 multi - function serial interface ch.0 (status) multi - function serial interface ch.0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5* 1 multi - function serial interface ch.1 (reception completed) 22 16 icr06 3a4 h 000fffa4 h 6* 1 mul ti - function serial interface ch.1 (status) multi - function serial interface ch.1 (transmission completed) 23 17 icr07 3a0 h 000fffa0 h 7* 1 multi - function serial interface ch.2 (reception completed) 24 18 icr08 39c h 000fff9c h 8* 1 multi - function serial interface ch.2 (status) multi - function serial interface ch.2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9* 1 d a t a s h e e t 156 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal multi - function serial interface ch.3 (reception completed) 26 1a icr10 394 h 000fff94 h 10* 1 multi - function serial interface ch.3 ( status) multi - function serial interface ch.3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 multi - function serial interface ch.4 (reception completed) 28 1c icr12 38c h 000fff8c h 12* 1 multi - function serial interface ch.4 (status) mul ti - function serial interface ch.4 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial interface ch.5 (reception completed) 30 1e icr14 384 h 000fff84 h 14* 1 multi - function serial interface ch.5 (status) multi - function serial interface ch.5 (transmission completed) 31 1f icr15 380 h 000fff80 h 15* 9 flexray0 multi - function serial interface ch.6 (reception completed) 32 20 icr16 37c h 000fff7c h 16* 1 multi - function serial interface ch.6 (status) flexray1 multi - function serial interface ch.6 (transmission completed) 33 21 icr17 378 h 000fff78 h 17* 10 flexray timer 0 can0 34 22 icr18 374 h 000fff74 h - can3 flexray timer 1 can1 35 23 icr19 370 h 000fff70 h - ram diagnosis completed ram in itialization completed e rror generation at ram diagnosis backup ram diagnosis completed backup ram initialization completed e rror generation at backup ram diagnosis ahb ram diagnosis completed ahb ram initializatio n completed error generation at ahb ram diagnosis can4 can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 up/down counter 1 can5 flexray pll gear/flexray pll alarm real time clock 37 25 icr21 368 h 000fff68 h - multi - function serial interface ch.7 (reception completed) 38 26 icr22 364 h 000fff64 h 22* 1 multi - function serial interface ch.7 (status) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 157 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal 16 - bit free - run timer 0 ( " 0 " detection) / (compare clear) 39 27 icr23 360 h 000fff60 h 23 multi - function se rial interface ch.7 (transmission completed) ppg0/1/10/11/20/21/30/31/40/41 40 28 icr24 35c h 000fff5c h 24* 3 16 - bit free - run timer 1 ( " 0 " detection) / (compare clear) ppg2/3/12/13/22/23/32/33/42/43 41 29 icr25 358 h 000fff58 h 25* 3 16 - bit free - run timer 2 ( " 0 " detection) / (compare clear) ppg4/5/14/15/24/25/34/35/44/45 42 2a icr26 354 h 000fff54 h 26* 3 ppg6/7/16/17/26/27/36/37/46/47 43 2b icr27 350 h 000fff50 h 27* 3 ppg8/9/18/19/28/29/38/39 44 2c icr28 34c h 000fff4c h 28* 3 multi - function s erial interface ch.8 (reception completed) 45 2d icr29 348 h 000fff48 h 29* 1 multi - function serial interface ch.8 (status) 16 - bit icu 0 (fetching) / 16 - bit icu 1 (fetching) main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer multi - function serial interface ch.8 (transmission completed) 16 - bit icu 2 (fetching) /16 - bit icu 3 (fetching) clock calibration unit (sub oscillation) 47 2f icr31 340 h 000fff40 h 31* 1 * 4 multi - function serial interface ch.9 (reception completed) multi - function serial interface ch.9 (status) a/d converter 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16 17/18/19/20/21/22/23/24/25/26/27/28/29/30/31 48 30 icr32 33c h 000fff3c h 32 clock calibration unit (cr oscillation) 49 31 icr33 33 8 h 000fff38 h 33 multi - function serial interface ch.9 (transmission completed) 16 - bit ocu 0 (match) / 16 - bit ocu 1 (match) 32 - bit free - run timer 4 50 32 icr34 334 h 000fff34 h 34* 6 16 - bit ocu 2 (match) / 16 - bit ocu 3 (match) 32 - bit free - run timer 3/5 51 33 icr35 330 h 000fff30 h 35* 6 16 - bit ocu 4 (match) / 16 - bit ocu 5 (match) 32 - bit icu6 (fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36* 1 multi - function serial interface ch.10 (reception completed) multi - function serial interface ch.10 (status) 32 - bit icu7 (fetching / measurement ) 53 35 icr37 328 h 000fff28 h 37 multi - function serial interface ch.10 (transmission completed) 32 - bit icu8 (fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38* 1 multi - function se rial interface ch.11 (reception completed) multi - function serial interface ch.11 (status) d a t a s h e e t 158 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal 32 - bit icu9 (fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg dead timer underflow 0 / 1/ 2 wg dead timer reload 0 / 1/ 2 wg dtti 0 32 - bit icu4 (fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch.11 (transmission completed) 32 - bit icu5 (fetching / measurement ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/35/36/37/38/39/40/41 /42/43/44/45/46/47 32 - bit ocu6/7/10/11 (match) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu8/9 (match) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 60 3c icr44 30c h 000fff0c h 44 base timer 0 irq1 base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45* 5 base timer 1 irq1 - - dmac0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delayed interrupt 63 3f icr47 300 h 000fff00 h - system reserved (used for realos) 64 40 - 2fc h 000ffefc h - system reserved (used for realos) 65 41 - 2f8 h 000ffef8 h - used with the int instruction. 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - * : it does not support the dma transfer request by the interrupt generated from a peripheral to which no rn (resource number) is assign ed. * 1: the status of the multi - function serial interface does not support the dma transfer by the i 2 c reception and flexray . * 2: the reload timer ch.4 to ch.7 does not support the dma transfer by the interrupt. * 3: the ppg ch.24 to ch. 8 7 does not suppo rt the dma transfer by the interrupt. * 4: the clock calibration unit does not support the dma transfer by the interrupt. * 5: it does not support the dma transfer by the interrupt because of the ram ecc bit error. * 6: the 32 - bit free - run timer ch.3 to ch . 10 does not support the dma transfer by the interrupt. * 8: it does not support the dma transfer by the external low - voltage detection interrupt. *9: it does not support the dma transfer by the flexray interrupt. *10: it does not support the dma transfe r by the flexray timer interrupt. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 159 confidential ? mb91f52xm (208 pin ) interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserve d 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reserved 13 0d - 3c8 h 000fffc8 h - exception of illegal instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15(f h ) fixed 3c0 h 000fffc0 h - error generation at internal bus diagnosis xbs ram double - bit error detection backup ram dou ble - bit error detection ahb ram double - bit error detection tpu violation external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1* 8 external low - voltage detection interrupt exter nal interrupt 16 - 23 reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2* 2 reload timer 2/3/6/7 19 13 icr03 3b0 h 000fffb0 h 3* 2 multi - function serial interface ch.0 (reception completed) 20 14 icr04 3ac h 000fffac h 4* 1 multi - function serial interface ch.0 (status) multi - function serial interface ch.0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5* 1 multi - function serial interface ch.1 (reception completed) 22 16 icr06 3a4 h 000fffa4 h 6* 1 multi - function serial interface ch.1 (status) multi - function serial interface ch.1 (transmission completed) 23 17 icr07 3a0 h 000fffa0 h 7* 1 multi - function serial interface ch.2 (reception completed) 24 18 icr08 39c h 000fff9c h 8* 1 multi - function serial interface ch.2 (status) multi - function serial interface ch.2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9* 1 d a t a s h e e t 160 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal multi - function serial interface ch.3 (reception completed) 26 1a icr10 394 h 000fff94 h 10* 1 multi - function serial interface ch.3 (status) multi - function serial interface ch.3 (transmission completed) 27 1b icr11 390 h 000fff90 h 11 multi - function serial interface ch.4 / ch.12 (reception completed) 28 1c icr12 38c h 000fff8c h 12* 1 multi - function serial interface ch.4 / ch.12 (status) multi - function serial interface ch.4 / ch.12 (transmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial interface ch.5 / ch.13 (reception completed) 30 1e icr14 384 h 000fff84 h 14* 1 multi - function serial interface ch.5 / ch.13 (status) multi - function serial interface c h.5 / ch.13 (transmission completed) 31 1f icr15 380 h 000fff80 h 15* 9 flexray0 multi - function serial interface ch.6 / ch.14 (reception completed) 32 20 icr16 37c h 000fff7c h 16* 1 multi - function serial interface ch.6 / ch.14 (status) flexray1 multi - function serial interface ch.6 / ch.14 (transmission completed) 33 21 icr17 378 h 000fff78 h 17* 10 flexray timer 0 can0 34 22 icr18 374 h 000fff74 h - can3 flexray timer 1 can1 35 23 icr19 370 h 000fff70 h - ram diagnosis complet ed ram initialization completed e rror generation at ram diagnosis backup ram diagnosis completed backup ram initialization completed e rror generation at backup ram diagnosis ahb ram diagnosis completed ahb r am initialization completed error generation at ahb ram diagnosis can4 can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 /2 up/down counter 1 /3 can5 flexray pll gear/flexray pll alarm real time clock 37 25 icr21 368 h 000fff68 h - multi - function serial interface ch.7 / ch.15 (reception completed) 38 26 icr22 364 h 000fff64 h 22* 1 multi - function serial interface ch.7 / ch.15 (status) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 161 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal 16 - bit free - run timer 0 ( " 0 " detection) / (compare clear) 39 27 icr23 36 0 h 000fff60 h 23 multi - function serial interface ch.7 / ch.15 (transmission completed) ppg0/1/10/11/20/21/30/31/40/41 /50/51/60/61 40 28 icr24 35c h 000fff5c h 24* 3 16 - bit free - run timer 1 ( " 0 " detection) / (compare clear) ppg2/3/12/13/22/23/32/ 33/42/43 /52/53/62/63 41 29 icr25 358 h 000fff58 h 25* 3 16 - bit free - run timer 2 ( " 0 " detection) / (compare clear) ppg4/5/14/15/24/25/34/35/44/45 /54/55 42 2a icr26 354 h 000fff54 h 26* 3 ppg6/7/16/17/26/27/36/37/46/47 /56/57 43 2b icr27 350 h 000fff50 h 27* 3 ppg8/9/18/19/28/29/38/39 /48/49/58/59 44 2c icr28 34c h 000fff4c h 28* 3 multi - function serial interface ch.8 / ch.16 (reception completed) 45 2d icr29 348 h 000fff48 h 29* 1 multi - function serial interface ch.8 / ch.16 (status) 16 - bit icu 0 (fetching) / 16 - bit icu 1 (fetching) main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer multi - function serial interface ch.8 / ch.16 (transmission completed) 16 - bit icu 2 (fetching) /16 - bit icu 3 (fetching) clock calibrati on unit (sub oscillation) 47 2f icr31 340 h 000fff40 h 31* 1 * 4 multi - function serial interface ch.9 / ch.17 (reception completed) multi - function serial interface ch.9 / ch.17 (status) a/d converter 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16 17/18/ 19/20/21/22/23/24/25/26/27/28/29/30/31 48 30 icr32 33c h 000fff3c h 32 clock calibration unit (cr oscillation) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch.9 / ch.17 (transmission completed) 16 - bit ocu 0 (match) / 16 - bit ocu 1 (ma tch) 32 - bit free - run timer 4 /6/8/10 50 32 icr34 334 h 000fff34 h 34* 6 16 - bit ocu 2 (match) / 16 - bit ocu 3 (match) 32 - bit free - run timer 3/5 /7/9 51 33 icr35 330 h 000fff30 h 35* 6 16 - bit ocu 4 (match) / 16 - bit ocu 5 (match) 32 - bit icu6 (fe tching / measurement ) 52 34 icr36 32c h 000fff2c h 36* 1 multi - function serial interface ch.10 / ch.18 (reception completed) multi - function serial interface ch.10 / ch.18 (status) 32 - bit icu7 (fetching / measurement ) 53 35 icr37 328 h 000fff28 h 37 multi - function serial interface ch.10 / ch.18 (transmission completed) 32 - bit icu8 (fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38* 1 multi - function serial interface ch.11 / ch.19 (reception completed) multi - function serial interface ch.1 1 / ch.19 (status) d a t a s h e e t 162 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal 32 - bit icu9 (fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg dead timer underflow 0 / 1/ 2 wg dead timer reload 0 / 1/ 2 wg dtti 0 32 - bit icu4 /10 (fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch.11 / ch.19 (transmission completed) 32 - bit icu5 /11 (fetching / measurement ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47 48/49/50/51/52/53/54/55/56/57/58/59/60/61/62/63 32 - bit ocu6/7/10/11 (match) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu8/9 /12/13 (match) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 60 3c icr44 30c h 000fff0c h 44 base timer 0 irq1 base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45* 5 base timer 1 irq1 - - dmac0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delayed interrupt 63 3f icr47 300 h 000fff00 h - system reserved (used for realos) 64 40 - 2fc h 000ffefc h - system reserved (used for realos) 65 4 1 - 2f8 h 000ffef8 h - used with the int instruction. 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - * : it does not support the dma transfer request by the interrupt generated from a peripheral to which no rn (resource number) is assigned. * 1: the status of the multi - function serial interface does not support the dma transfer by the i 2 c reception and flexray . * 2: the reload timer ch.4 to ch.7 does not support the dma transfer by the interrupt. * 3: the ppg ch.24 to ch. 8 7 does not support the dma t ransfer by the interrupt. * 4: the clock calibration unit does not support the dma transfer by the interrupt. * 5: it does not support the dma transfer by the interrupt because of the ram ecc bit error. * 6: the 32 - bit free - run timer ch.3 to ch. 10 does not support the dma transfer by the interrupt. * 8: it does not support the dma transfer by the external low - voltage detection interrupt. *9: it does not support the dma transfer by the flexray interrupt. *10: it does not support the dma transfer by the fle xray timer interrupt. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 163 confidential ? mb91f52xy (416 pin ) interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal reset 0 0 - 3fc h 000ffffc h - system reserved 1 1 - 3f8 h 000ffff8 h - system reserved 2 2 - 3f4 h 000ffff4 h - system reserved 3 3 - 3f0 h 000ffff0 h - system reserved 4 4 - 3ec h 000fffec h - fpu exception 5 5 - 3e8 h 000fffe8 h - exception of instruction access protection violation 6 6 - 3e4 h 000fffe4 h - exception of data access protection violation 7 7 - 3e0 h 000fffe0 h - data access error interrupt 8 8 - 3dc h 000fffdc h - inte instruction 9 9 - 3d8 h 000fffd8 h - instruction break 10 0a - 3d4 h 000fffd4 h - system reserved 11 0b - 3d0 h 000fffd0 h - system reserved 12 0c - 3cc h 000fffcc h - system reser ved 13 0d - 3c8 h 000fffc8 h - exception of illegal instruction 14 0e - 3c4 h 000fffc4 h - nmi request 15 0f 15(f h ) fixed 3c0 h 000fffc0 h - error generation at internal bus diagnosis xbs ram double - bit error detection backup ram double - bit erro r detection ahb ram double - bit error detection tpu violation external interrupt 0 - 7 16 10 icr00 3bc h 000fffbc h 0 external interrupt 8 - 15 17 11 icr01 3b8 h 000fffb8 h 1* 8 external low - voltage detection interrupt external interrup t 16 - 23 reload timer 0/1/4/5 18 12 icr02 3b4 h 000fffb4 h 2* 2 reload timer 2/3/6/7 19 13 icr03 3b0 h 000fffb0 h 3* 2 multi - function serial interface ch.0 (reception completed) 20 14 icr04 3ac h 000fffac h 4* 1 multi - function serial interface ch.0 (status ) multi - function serial interface ch.0 (transmission completed) 21 15 icr05 3a8 h 000fffa8 h 5* 1 multi - function serial interface ch.1 (reception completed) 22 16 icr06 3a4 h 000fffa4 h 6* 1 multi - function serial interface ch.1 (status) multi - fun ction serial interface ch.1 (transmission completed) 23 17 icr07 3a0 h 000fffa0 h 7* 1 multi - function serial interface ch.2 (reception completed) 24 18 icr08 39c h 000fff9c h 8* 1 multi - function serial interface ch.2 (status) multi - function serial inter face ch.2 (transmission completed) 25 19 icr09 398 h 000fff98 h 9* 1 d a t a s h e e t 164 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal multi - function serial interface ch.3 (reception completed) 26 1a icr10 394 h 000fff94 h 10* 1 multi - function serial interface ch.3 (status) multi - function serial interface ch.3 (transm ission completed) 27 1b icr11 390 h 000fff90 h 11 multi - function serial interface ch.4 / ch.12 (reception completed) 28 1c icr12 38c h 000fff8c h 12* 1 multi - function serial interface ch.4 / ch.12 (status) multi - function serial interface ch.4 / ch.12 (tra nsmission completed) 29 1d icr13 388 h 000fff88 h 13 multi - function serial interface ch.5 / ch.13 (reception completed) 30 1e icr14 384 h 000fff84 h 14* 1 multi - function serial interface ch.5 / ch.13 (status) multi - function serial interface ch.5 / ch.13 ( transmission completed) 31 1f icr15 380 h 000fff80 h 15* 9 flexray0 multi - function serial interface ch.6 / ch.14 (reception completed) 32 20 icr16 37c h 000fff7c h 16* 1 multi - function serial interface ch.6 / ch.14 (status) flexray1 multi - fu nction serial interface ch.6 / ch.14 (transmission completed) 33 21 icr17 378 h 000fff78 h 17* 10 flexray timer 0 can0 34 22 icr18 374 h 000fff74 h - can3 flexray timer 1 can1 35 23 icr19 370 h 000fff70 h - ram diagnosis completed ra m initialization completed e rror generation at ram diagnosis backup ram diagnosis completed backup ram initialization completed e rror generation at backup ram diagnosis ahb ram diagnosis completed ahb ram initializ ation completed error generation at ahb ram diagnosis can4 can2 36 24 icr20 36c h 000fff6c h - up/down counter 0 /2 up/down counter 1 /3 can5 flexray pll gear/flexray pll alarm real time clock 37 25 icr21 368 h 000fff68 h - multi - function serial interface ch.7 / ch.15 (reception completed) 38 26 icr22 364 h 000fff64 h 22* 1 multi - function serial interface ch.7 / ch.15 (status) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 165 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal 16 - bit free - run timer 0 ( " 0 " detection) / (compare clear) 39 27 icr23 360 h 000fff60 h 23 multi - function serial interface ch.7 / ch.15 (transmission completed) ppg 0/1/10/11/20/21/30/31/40/41 /50/51/60/61 / 70/71/80/81 40 28 icr24 35c h 000fff5c h 24* 3 16 - bit free - run timer 1 ( " 0 " detection) / (compare clear) ppg 2/3/12/13/22/23/3 2/33/42/43 /52/53/62/63 /72/73/82/83 41 29 icr25 358 h 000fff58 h 25* 3 16 - bit free - run timer 2 ( " 0 " detection) / (compare clear) ppg 4/5/14/15/24/25/34/35/44/45 /54/55 /64/65/74/75/84/85 42 2a icr26 354 h 000fff54 h 26* 3 ppg 6/7/16/17/26/27/36/37/46/47 /56 /57 /66/67/76/77/86/87 43 2b icr27 350 h 000fff50 h 27* 3 ppg 8/9/18/19/28/29/38/39 /48/49/58/59 /68/69/78/79 44 2c icr28 34c h 000fff4c h 28* 3 multi - function serial interface ch.8 / ch.16 (reception completed) 45 2d icr29 348 h 000fff48 h 29* 1 multi - function seri al interface ch.8 / ch.16 (status) 16 - bit icu 0 (fetching) / 16 - bit icu 1 (fetching) main timer 46 2e icr30 344 h 000fff44 h 30 sub timer pll timer multi - function serial interface ch.8 / ch.16 (transmission completed) 16 - bit icu 2 (fetching) /16 - bit icu 3 (fetching) clock calibration unit (sub oscillation) 47 2f icr31 340 h 000fff40 h 31* 1 * 4 multi - function serial interface ch.9 / ch.17 (reception completed) multi - function serial interface ch.9 / ch.17 (status) a/d converter 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16 17/18/19/20/21/22/23/24/25/26/27/28/29/30/31 48 30 icr32 33c h 000fff3c h 32 clock calibration unit (cr oscillation) 49 31 icr33 338 h 000fff38 h 33 multi - function serial interface ch.9 / ch.17 (trans mission completed) 16 - bit ocu 0 (match) / 16 - bit ocu 1 (match) 32 - bit free - run timer 4 /6/8/10 50 32 icr34 334 h 000fff34 h 34* 6 16 - bit ocu 2 (match) / 16 - bit ocu 3 (match) 32 - bit free - run timer 3/5 /7/9 51 33 icr35 330 h 000fff30 h 35* 6 1 6 - bit ocu 4 (match) / 16 - bit ocu 5 (match) 32 - bit icu6 (fetching / measurement ) 52 34 icr36 32c h 000fff2c h 36* 1 multi - function serial interface ch.10 / ch.18 (reception completed) multi - function serial interface ch.10 / ch.18 (status) 32 - bit icu7 (fetching / measurement ) 53 35 icr37 328 h 000fff28 h 37 multi - function serial interface ch.10 / ch.18 (transmission completed) 32 - bit icu8 (fetching / measurement ) 54 36 icr38 324 h 000fff24 h 38* 1 multi - function serial interface ch.11 / ch.19 (reception completed) multi - function serial interface ch.11 / ch.19 (status) d a t a s h e e t 166 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential interrupt factor interrupt number interrupt level offset default address for tbr rn * decimal hexa - decimal 32 - bit icu9 (fetching / measurement ) 55 37 icr39 320 h 000fff20 h 39 wg dead timer underflow 0 / 1/ 2 wg dead timer reload 0 / 1/ 2 wg dtti 0 32 - bi t icu4 /10 (fetching / measurement ) 56 38 icr40 31c h 000fff1c h 40 multi - function serial interface ch.11 / ch.19 (transmission completed) 32 - bit icu5 /11 (fetching / measurement ) 57 39 icr41 318 h 000fff18 h 41 a/d converter 32/33/34/35/36/37/38/39/40/41/ 42/43/44/45/46/47 48/49/50/51/52/53/54/55/56/57/58/59/60/61/62/63 32 - bit ocu6/7/10/11 (match) 58 3a icr42 314 h 000fff14 h 42 32 - bit ocu8/9 /12/13 (match) 59 3b icr43 310 h 000fff10 h 43 base timer 0 irq0 60 3c icr44 30c h 000fff0c h 44 base timer 0 irq 1 base timer 1 irq0 61 3d icr45 308 h 000fff08 h 45* 5 base timer 1 irq1 - - dmac0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15 62 3e icr46 304 h 000fff04 h - delayed interrupt 63 3f icr47 300 h 000fff00 h - system reserved (used for realos) 64 40 - 2fc h 000ffefc h - system reserved (used for realos) 65 41 - 2f8 h 000ffef8 h - used with the int instruction. 66 | 255 42 | ff - 2f4 h | 000 h 000ffef4 h | 000ffc00 h - * : it does not support the dma transfer request by the interrupt generated from a peripheral to which no rn (resource number) is assigned. * 1: the status of the multi - function serial interface does not support the dma transfer by the i 2 c reception and flexray . * 2: the reload timer ch.4 to ch.7 does not support the dma transfer by the interrupt. * 3: the ppg ch.24 to ch. 8 7 does not support the dma transfer by the interrupt. * 4: the clock calibration unit does not support the dma transfer by the interrupt. * 5: it does not support the dma transfer by the interrupt because of the ram ecc bit error. * 6: the 32 - bit free - run timer ch.3 to ch. 10 does not support the dma transfer by the interrupt. * 8: it does not support the dma transfer by the external low - voltage detection interrupt. *9: it does not support the dma transfer by the flexray interrupt. *10: it does not support the dma transfer by the flexray timer interrupt. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 167 confidential ? electrical characteristics 1. absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1 , * 2 v cc v ss - 0. 3 v ss +6. 0 v v cc e v ss - 0. 3 v cc v analog power supply voltage * 1 , * 2 av cc v ss - 0. 3 v ss +6. 0 v av rh av cc v cc anal og reference voltage * 1 avrh v ss - 0. 3 v ss +6. 0 v avrh av cc input voltage * 1 v i v ss - 0. 3 v cc +0. 3 v when vcce pin is a power supply *9 v ss - 0. 3 v cc e +0. 3 analog pin input voltage * 1 v ia5 v ss - 0. 3 v cc +0. 3 v v ss - 0. 3 v cc e +0. 3 v when vcce pin is a power s upply *9 out put voltage * 1 v o v ss - 0. 3 v cc +0. 3 v maximum clamp current i clamp - 4.0 ma * 6 total maximum clamp current |i clamp | - 2 0 ma * 6 " l " level maximum output current * 3 i ol1 - 15 ma i ol2 - 30 ma " l " level average output current * 4 i olav1 - 4 ma i olav2 - 12 ma "l" level total output current * 5 i ol1 - 100 ma i ol2 - 120 ma "h" level maximum output current * 3 i oh1 - - 15 ma i oh2 - - 30 ma "h" level average output current * 4 i ohav1 - - 4 ma i ohav2 - - 12 ma "h" level total output c urrent * 5 i oh1 - - 100 ma i oh2 - - 120 ma power consumption t a : - 40 c to + 105 c p d - 990 mw *8 t a : - 40 c to + 125 c - 990 mw *8, *10 - 780 mw *8, *12 755 mw *8, *11 operating temperature t a - 40 +1 0 5 c - 40 +1 2 5 c * 7 storage temperatu re tstg - 55 +150 c *1 : these parameters are based on the condition that v ss =av ss =0.0v * 2 : caution must be taken th at av cc , avrh and v cce do not exceed v cc upon power - on and under other circumstances. * 3 : the m aximum output current is defined as the val ue of the peak current flowing through any one of the corresponding pins. * 4 : the a verage output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. the average value is the operation current the operation ratio. * 5: the total output current is defined as the maximum current value flowing through all of corresponding pins. d a t a s h e et 168 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential * 6 : corresponding pins: all general - purpose ports except p035, 041, 093, 122 , p222, p227, p232 and p236 . us e within recommended operating conditions. use at dc voltage (current). the + b signal should always be applied by connecting a limiting resistor between the + b signal and the microcontroller. the value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the + b signal is input. note that when the microcontroller drive current is low, such as in the low power consumption modes, the + b input potential can increase the potential at the v cc pin via a protective diode, possibly affecting other devices. note that if the + b signal is input when the microcontroller is off (not fixed at 0 v), since the power is supplied throu gh the pin, the microcontroller may operate incompletely. note that if the +b signal is input at power - on, since the power is supplied through the pin, the power - on reset may not function in the power supply voltage. do not leave + b input pins open. * 7: when it is used under this condition , contact your sales representative. * 8: it is a standard when four - layer substrate is used. *9: please see to the item of " product lineup " for details. *10: it is a condition that can be used by limiting the product type of teqfp and bga. *11: it is a condition that can be used by the package limitation of fpt - 144p - m08 and fpt - 176p - m07 . *12: it is a condition that can be used by limiting the package of fpt - 208p - m06. sample recommended circuit < warning > semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. mb915 2 0 series + b input (12 to 16v) protective diode limiting resistor current d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 169 confidential 2. recommended operating c onditions (v ss =av ss =0.0v) parameter symbol value unit remarks min max power supply voltage v cc v cc e av cc 4.5 5.5 v recommended operation guarantee range ( when 5.0v is used) 3 . 0 3 . 6 v recommended operation guarantee range ( when 3.3v is used) 2.7 5.5 v operation guarantee range * 1 smoothing capacitor * 2 c s 4.7 ( tolerance within 50 % ) f use a ceramic capacitor or a capacitor that has the similar frequency characteristics. use a capacitor with a capacitance greater than c s as the smoothing capacito r on the vcc pin. operating temperature t a - 40 +1 0 5 c - 40 +1 2 5 c * 3 * 1: when it is used outside recommended operation guarantee range (range of the operation guarantee) ,contact your sales representative. moreover, minimum value with an effective ex ternal low - voltage detection reset becomes a voltage until generating low - voltage detection reset. * 2 : see the following diagram for details on the connection of smoothing capacitor c s . * 3: when it is used under this condition , contact your sales represent ative. ? < warning > the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted wh en the device is operated under these conditions. any use of semiconductor devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. c s c v ss av ss v ss d a t a s h e et 170 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential 3. dc characteristics (t a : - 40 c to + 105 c , v cc = avcc= 5 . 0 v 10% / v cc = avcc= 3 . 3 v 0 . 3 v ,v ss =av ss =0.0v) para meter symb ol pin name conditions value unit remarks min typ max power supply current i cc 5 vcc operating frequency f cp = 128 mhz, fcpp= 32 mhz, * 3 at normal operation - 85 122 ma operating frequency f cp = 128 mhz, fcpp= 32 mhz, * 3 at flash write * 2 - 95 135 ma operating frequency f cp = 128 mhz, fcpp= 32 mhz, * 3 at flash erase * 2 - 95 135 ma operating frequency f cp =80mhz, fcpp=40mhz, at n ormal operation - 80 117 ma operating frequency f cp =80mhz, fcpp=40mhz, at flash write * 2 - 90 130 ma operating frequency f cp =80mhz, fcpp=40mhz, at flash erase * 2 - 90 1 30 ma operating frequency f cp =64mhz, fcpp=32mhz, at normal operation - 73 1 10 ma operating frequency f cp =64mhz, fcpp=32mhz, at flash write * 2 - 83 1 23 ma operating frequency f cp =64mhz, fcpp=32mhz, at flash erase * 2 - 83 1 23 ma operating frequency f cp =48mhz, fcpp=24mhz, at normal operation - 53 1 00 ma operati ng frequency f cp =48mhz, fcpp=24mhz, at flash write * 2 - 63 1 13 ma operating frequency f cp =48mhz, fcpp=24mhz, at flash erase * 2 - 63 1 13 ma i ccs 5 operating frequency f cp =80mhz, fcpp=40mhz, at cpu sleep mode - 57 94 ma i ccbs 5 operating frequenc y f cp =80mhz, fcpp=40mhz, at bus sleep mode - 39 79 ma i cct 5 watch mode when using crystal 4mhz t a =+25 c * 1 - 2000 3600 a when using built - in cr clock 50khz t a =+25 c * 1 - 640 2440 when using sub clock 32khz t a =+25 c * 1 - 660 2460 i cc h 5 stop mode t a =+25 c * 1 - 640 2440 a d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 171 confidential para meter symb ol pin name conditions value unit remarks min typ max power supply current i cct 52 vcc watch mode (p ower off ) when using crystal 4mhz t a =+25 c * 1 - 1400 1600 a lvd/ rtc operation , backup ram 16 kb retention when using built - in cr clock 50khz , t a =+25 c * 1 - 63 203 when using sub clock 32khz t a =+25 c * 1 - 80 220 i cch 52 stop mode (p ower off ) t a =+25 c * 1 - 60 200 a backup ram 16 kb retention d a t a s h e et 172 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ( t a : - 40 c to + 1 2 5 c , v cc = avcc= 5 . 5 v 10% / v cc = avcc= 3 . 3 v 0 . 3 v ,v ss =av ss =0.0v ) para meter symb ol pin name conditions value unit remarks min typ max power supply current i cc 5 vcc operating frequency f cp = 128 mhz, fcpp= 32 mhz, * 3 at normal operation - 85 122 ma operating frequency f cp = 128 mhz, fcpp= 32 mhz, * 3 at flash write * 2 - 95 135 ma operating frequency f cp = 128 mhz, fcpp= 32 mhz, * 3 at flash erase * 2 - 95 135 ma operating frequency f cp =80mhz, fcpp=40mhz, at normal operation - 80 117 ma operating frequency f cp =80mhz, fcpp= 40mhz, at flash write * 2 - 90 130 ma operating frequency f cp =80mhz, fcpp=40mhz, at flash erase * 2 - 90 130 ma operating frequency f cp =64mhz, fcpp=32mhz, at normal operation - 73 110 ma operating frequency f cp =64mhz, fcpp=32mhz, at flash writ e * 2 - 83 123 ma operating frequency f cp =64mhz, fcpp=32mhz, at flash erase * 2 - 83 123 ma operating frequency f cp =48mhz, fcpp=24mhz, at normal operation - 53 100 ma operating frequency f cp =48mhz, fcpp=24mhz, at flash write * 2 - 63 113 ma operating frequency f cp =48mhz, fcpp=24mhz, at flash erase * 2 - 63 113 ma i ccs 5 operating frequency f cp =80mhz, fcpp=40mhz, at cpu sleep mode - 57 94 ma i ccbs 5 operating frequency f cp =80mhz, fcpp=40mhz, at bus sleep mode - 39 79 ma i cct 5 watc h mode when using crystal 4mhz t a =+25 c * 1 - 2000 3600 a when using built - in cr clock 50khz t a =+25 c * 1 - 640 2440 when using sub clock 32khz t a =+25 c * 1 - 660 2460 i cch 5 stop mode t a =+25 c * 1 - 640 2440 a d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 173 confidential para meter symb ol pin name conditions value unit remarks min typ max power supply current i cct 52 vcc watch mode (p ower off ) when using crystal 4mhz t a =+25 c * 1 - 1400 1600 a lvd/ rtc operation , backup ram 16 kb retention when using built - in cr clock 50khz , t a =+25 c * 1 - 63 203 when using sub clock 32khz t a =+25 c * 1 - 80 220 i cch 52 stop mode (p ower off ) t a =+25 c * 1 - 60 200 a backup ram 16 kb retention * 1 : it is a standard in bramsc (backup ram sleep control bit)=1(enter the state of the sleep at the standby mode) condition. * 2 : it is a prohibition two flash or more writing/erasing the flash and the workflash for the internally stored program at the same time. * 3 : there is a frequency limitation by the product type. please see "4. ac characteristics" for deta ils. d a t a s h e et 174 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (t a : - 40 c to + 1 2 5 c , v cc = av cc = 5.0v 10% /vcc=av cc =3.3v 0.3v ,v ss =av ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max input leak current i il all input pins v cc =av cc =5.5v v ss d a t a s h e et 176 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential parameter symbol pin name conditions value unit remarks min typ max l level input voltage * 1 v il1 p000,002,003, 005,020,022, 024,026,035, 041,045,055, 057,071 - 077, 081,082,093, 096,097, 100 - 102,111, 115, 116,122, 1 26,130,134, 150,151,153, 200 - 202,204 - 2 06,210 - 212,21 4 - 216,220 - 222 ,225 - 227,230 - 232,234 - 236, tck,tdi,tm s,trst cmos hysteresis input level vss - 0.3 v cc v v il 2 p001,004,006, 007,010 - 017, 052,114,120, 123,155 cmos hysteresis input level vss - 0. 3 v cc v v il3 automotive input level vss - 0. 5 v cc v v il 4 port other than v ih1 , v ih 2 , v ih 3 automotive input level vss - 0. 5 v cc v v il5 rstx,nmix, md0,md1 cmos hysteresis input level vss - 0. 2 v cc v v ilt debugif ttl input level vss - 0. 8 v * 1 : it is pro vided by v cce for the pin corresponding to the v cce power supply instead of v cc . please see " product lineup " for details. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 177 confidential 4. ac characteristics (1) main clock timing (t a : - 40 c to + 1 2 5 c ,v cc = av cc = 5.0v 10% / v cc = av cc =3 . 3 v 0.3v ,v ss =av ss =0.0v ) parameter sym bol pin name con ditio ns value unit remarks min typ max source oscillation clock frequency f c x0, x1 - - 4 16 mhz source oscillation clock cycle time t cyl x0, x1 62.5 250 - ns internal operating clock frequency *1 f cp - 2 - 128 mhz cpu clock * 3 f c p p 1 40 peripheral bus clock f cp t 1 40 external bus clock (when v cc =5.0v is used) * 2 1 32 external bus clock (when v cc =3.3v is used) internal operating clock cycle time *1 t cp - 7 . 82 - 500 ns cpu clock * 4 t c p p 25 1000 periphera l bus clock t cp t 25 1000 external bus clock (when v cc =5.0v is used) 31.25 1000 external bus clock (when v cc =3.3v is used) can pll jitter ( during lock ) t pj - - 10 - 10 ns f c p =80 mhz (4mhz ? cc r - 50 100 150 khz * 1 : the maximum / minimum value is defined when using the main clock and pll clock. *2: please use it with external load capacity 12pf or less for vcc=3.3v0.3v (40mhz operation). *3: mb91f52xr/mb91f52xu (lqfp) is 80mhz or less. mb 9 1f52xr/mb91f52xu(teqfp) and mb91f52xm/mb91f52xy is 128mhz or less. *4: mb91f52xr/mb91f52xu (lqfp) is 12.5ns or more. mb91f52xr/mb91f52xu(tedfp) and mb91f52xm/mb91f52xy is 7.82ns or more. ? x0,x1 c lock timing x0 t cyl d a t a s h e et 178 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? can pll jitter deviation time from the ideal clock is assured per cycle out of 20, 000 cycles. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 179 confidential (1 - 2) sub clock timing (t a : - 4 0 c to + 1 2 5 c ,v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min typ max source oscillation clock frequency f c l x0 a , x1 a - - 32.768 - khz source oscillation clock cycle time t lc yl x0 a , x1 a - 30.52 - s ? x0a,x1a clock timing x0a t lcyl d a t a s h e et 180 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? guaranteed operation range internal operation clock frequency vs. power supply voltage note: the power supply voltage, which is the low - voltage detection setting voltage or lower, is in the reset state. oscillation clock frequency vs. internal operation clock frequency internal operation clock frequency main clock pll clock multipli ed by 1 multipli ed by 2 multipli ed by 3 multipli ed by 4 ... multipli ed by 31 multip li ed by 32 oscillation clock frequency 4mhz 2mhz 4mhz 8mhz 12mhz 16mhz ... 124 mhz 128 mhz ? example of oscillation circuit note: as to the product with its clock supervisor s initial value is on , when the oscillat or is unable to start within 20ms from the stop state the clock supervisor will detect the oscillatio n stop. as a result, the cpu moves to the fail safe operation . design your print circuit board so that the oscillat or can start oscillation within 20ms. moreover, it is recommended to be designed after the match evaluation of the circuit is requested to th e departure pendulum maker when the oscillation circuit is composed. internal operation clock frequency f cp (mhz) 80(mb9 1f52xr/mb91f52xu ( lqfp ) ) 4 2 2.7 5.5 power supply voltage v cc (v) mb91f5 2 x guaranteed operation range pll guaranteed operation range 4.5 mb91f5 2 x recommended guaranteed operation range 128( mb91f52xr/mb91f52xu ( teqfp ) , m b91f52xm/mb91f52xy) 3.6 3.0 x1 x0 r=0 c2= 10 pf c1= 10 pf 4mhz d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 181 confidential ac characteristics are specified by the following measurement reference voltage values. ? input signal waveform ? output signal waveform hysteresis input pin (automotive) output pin h ysteresis input pin (cmos schmitt) 0.5vcc 0.8vcc 0.8v 2.4v 0.3vcc 0.7vcc d a t a s h e et 182 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (2) reset input (t a : - 40 c to + 1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v , v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max reset input time t rstl rstx C C + 100 C C C between several hundred s and several ms, and for an external clock, the time is 0 ms. ? at stop mode 0.2 v cc 100 s rstx x0 90% of amplitud e internal operation clock oscillation time of oscillator oscillation stabilization waiting time instruction execution inter nal reset 0.2 v cc t rstl rstx 0.2 v cc 0.2 v cc t rstl d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 183 confidential (3 ) power - on conditions (t a : - 40 c to + 1 2 5 c , v ss =0.0v) parameter symbol pin name conditions value unit remarks min typ max level detection voltage C cc C C cc C C C C C C C C C cc v cc = at level detection release level time C C off v cc C C C d a t a s h e et 184 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ( 4 ) multi - function serial ( 4 - 1 ) csio timing (4 - 1 - 1) bit setting: smr: md2=0, smr: md1=1, smr : md0=0, smr: scinv=0 , scr:spi=0 (t a : - 40 c to + 1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter symbol pin name cond itions value unit remarks min max serial cl ock cycle time t scyc sck0 to sck19 - 4t cp p - ns internal shift clock mode output pin : c l = 5 0pf sck slov i sck0 to sck2, sck5 to sck19 sot0 to sot2, sot5 to sot19 - 30 30 ns sck 3, sck 4 sot 3, sot 4 - 300 300 ns valid sin setup time t ivsh i sck0 to sck2, sck5 to sck 19 sin0 to sin2, sin5 to sin19 34 - ns sck 3, sck 4 sin 3, sin 4 300 - ns sck shix i sck0 to sck19 sin0 to sin19 0 - ns serial clock "h"pulse width t shsl sck0 to sck19 - t cp p +10 - ns external shift clock mode output pin: c l = 5 0pf serial clock "l" pulse width t slsh 2t cp p - 10 - ns sck slov e sck0 to sck2, sck5 to sck19 sot0 to sot2, sot5 to sot19 - 33 ns sck 3, sck 4 sot 3, sot 4 - 300 ns valid sin setup time t ivsh e sck0 to sck19 sin0 to sin19 10 - ns sck shix e 20 - ns sck fall time t f sck0 to sck19 - 5 ns sck rise time t r sck0 to sck19 - 5 ns notes : ac characteristic in clk synchronized mode. c l is the load capacitance applied to pins during testing. the maximum bard rate is limited by internal operation clock u sed and other parameters. please use ch.3 and ch.4 with maximum baud rate 400kbps or less. see hardware manual for details. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 185 confidential ? internal shift clock mode ? external shift clock mode 2.4v 2.4v 0.8v 0.8v sinx sotx sckx t scyc t slovi t shixi t ivshi 0.8v v ih 1 v i l 1 v ih 1 v i l 1 2.4v v ih 1 0.8v sinx sotx sckx t slsh t slove t shixe t ivshe t shsl v il 1 t f t r v ih 1 v il 1 v ih 1 v il 1 v ih 1 v il 1 d a t a s h e et 186 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (4 - 1 - 2 ) bit setting: smr: md2=0, smr: md1=1, smr : md0=0, smr: scinv= 1 , scr:spi=0 (t a : - 40 c to + 1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter symbol pin name cond itions value unit remarks min max serial clock cycle time t scyc sck0 to sck19 - 4t cp p - ns internal shift clock mode output pin : c l = 5 0pf sck s h ov i sck0 to sck2, sck5 to sc k19 sot0 to sot2, sot5 to sot19 - 30 30 ns sck 3, sck 4 sot 3, sot 4 - 300 300 ns valid sin setup time t ivs li sck0 to sck2, sck5 to sck 19 sin0 to sin2, sin5 to sin19 34 - ns sck 3, sck 4 s in3, s in4 300 - ns sck s l ix i sck0 to sck 19 sin0 to sin19 0 - ns serial clock "h"pulse width t shsl sck0 to sck19 - t cp p +10 - ns external shift clock mode output pin: c l = 5 0pf serial clock "l" pulse width t slsh 2t cp p - 10 - ns sck s h ov e sck0 to sck2, sck5 t o sck19 sot0 to sot2, sot5 to sot19 - 33 ns sck 3, sck 4 sot 3, sot 4 - 300 ns valid sin setup time t ivs le sck0 to sck19 sin0 to sin19 10 - ns sck s l ix e 20 - ns sck fall time t f sck0 to sck19 - 5 ns sck rise t ime t r sck0 to sck19 - 5 ns notes: ac characteristic in clk synchronized mode. c l is the load capacitance applied to pins during testing. the maximum bard rate is limited by internal operation clock used and other parameters. please use ch.3 and ch.4 with maximum baud rate 400kbps or less. see hardware manual for details. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 187 confidential ? internal shift clock mode ? external shift clock mode 2.4v 0.8 v 2.4 v 0.8v sinx sotx sckx t scyc t s h ovi t s l ixi t ivs l i 2.4 v v ih 1 v i l 1 v ih 1 v i l 1 2.4v v ih 1 0.8v sinx sotx sckx t s h s l t s h ove t s l ixe t ivs l e t s l s h v il 1 t r t f v ih 1 v il 1 v ih 1 v il 1 v ih 1 v il 1 d a t a s h e et 188 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (4 - 1 - 3) bit setting : smr : md2=0, smr:md1=1, smr : md0=0 , smr:scinv=0, scr:spi=1 (t a : - 40 c to + 1 2 5 c ,v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max serial clock cycle time t scyc sck0 to sck19 - 4t cp p - ns internal shift clock mode output pin : c l = 5 0pf sck s h ov i sck0 to sck2, sck5 to sck19 sot0 to sot2, sot5 to sot19 - 30 30 ns sck 3, sck 4 sot 3, sot 4 - 300 300 ns valid sin setup time t ivs li sck0 to sck2, sck5 to sck 19 sin0 to sin2, sin5 to sin19 34 - ns sck 3, sck 4 sin 3, sin 4 300 - ns sck s l ix i sc k0 to sck 19 sin0 to sin19 0 - ns sot s ovli sck0 to sck19 sot0 to sot19 2t cp p - 30 - ns serial clock "h"pulse width t shsl sck0 to sck19 - t cp p +10 - ns external shift clock mode output pin: c l = 5 0pf serial clock "l" pulse width t slsh 2t cp p - 10 - ns sck s h ov e sck0 to sck2, sck5 to sck19 sot0 to sot2, sot5 to sot19 - 33 ns sck 3, sck 4 sot 3, sot 4 - 300 ns valid sin setup time t ivsh e sck0 to sck19 sin0 to sin19 10 - ns sck s l ix e 20 - ns sck fall time t f sck0 to sck19 - 5 ns sck rise time t r sck0 to sck19 - 5 ns notes: ac characteristic in clk synchronized mode. c l is the load capacitance applied to pins during testing. the maximum bard rate is limited by internal o peration clock used and other parameters. please use ch.3 and ch.4 with maximum baud rate 400kbps or less. see hardware manual for details. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 189 confidential ? internal shift clock mode ? external shift clock mode *: it writes in the tdr register and, then, it changes. t ivshe t scyc t shovi t sovli t slixi t ivsli 2.4v 2.4v 0.8v 0.8v v ih v il v ih v il 2.4v 0.8v 0.8v sckx sotx sinx t slsh t shsl t shove t r t f t slixe t ivsle 2.4v 0.8v v ih v il v il v il v il v ih v ih v ih v ih v il 2.4v 0.8v sckx * sotx sinx d a t a s h e et 190 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (4 - 1 - 4) bit setting : smr : md2=0, smr:md1=1, smr : md0=0 , smr:scinv=1, scr:spi=1 (t a : - 40 c to + 1 2 5 c ,v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max serial clock cycle time t scyc sck0 to sck19 - 4t cp p - ns internal shift clock mode output pin : c l = 5 0pf sck s l ov i sck0 to sck2, sck5 to sck 19 sot0 to sot2, sot5 to sot19 - 30 30 ns sck 3, sck 4 sot 3, sot 4 - 300 300 ns valid sin sck ivs hi sck0 to sck2, sck5 to sck 19 sin0 to sin2, sin5 to sin19 34 - ns sck 3, sck 4 sin 3, sin 4 300 - ns sck s h ix i sck 0 to sck19 sin0 to sin19 0 - ns sot s ovhi sck0 to sck19 sot0 to sot19 2t cp p - 30 - ns serial clock "h"pulse width t shsl sck0 to sck19 - t cp p +10 - ns external shift clock mode output pin: c l = 5 0pf serial clock "l" pulse width t slsh 2t cp p - 10 - ns sck s l ov e sck0 to sck2, sck5 to sck19 sot0 to sot2, sot5 to sot19 - 33 ns sck 3, sck 4 sot 3, sot 4 - 300 ns valid sin sck ivsh e sck0 to sck19 sin0 to sin19 10 - ns sck shix e 2 0 - ns sck fall time t f sck0 to sck19 - 5 ns sck rise time t r sck0 to sck19 - 5 ns notes: ac characteristic in clk synchronized mode. c l is the load capacitance applied to pins during testing. the maximum bard rate is limited by internal operatio n clock used and other parameters. please use ch.3 and ch.4 with maximum baud rate 400kbps or less. see hardware manual for details. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 191 confidential ? internal shift clock mode ? external shift clock mode *: it writes in the tdr register and, then, it changes. t f t scyc t slovi t sovhi t shixi t ivshi 2.4v 2.4v 2.4v 0.8v 0.8v v ih v il v ih v il 2.4v 0.8v sckx sotx sinx t slsh t shsl t slove t r t f t shixe t ivshe 2.4v 0.8v v ih v il v il v il v il v ih v ih v ih v ih v il 2.4v 0.8v sckx * sotx sinx d a t a s h e et 192 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (4 - 1 - 5) bit setting : smr:md2=0, smr:md1=1, smr:md0=0 , when serial chip select is used : s cscr:csen=1, serial clock output mark level "h " : smr,scsfr:scinv=0, serial chip select inactive level "h" : scscr,scsfr:cslvl=1 (t a : - 40 c to + 1 2 5 c ,v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter sym bol pin name con ditio n s value unit remarks min max scssck cssi sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs 19 - t cssu - 5 0 *1 t cssu +0 *1 ns internal shift clock mode output pin : c l = 5 0pf sck 3, sck4 scs3, scs40 to scs43 t cssu - 5 0 *1 t cssu + 30 0 *1 ns sckscs cs hi sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs 19 t cshd - 1 0 *2 t cshd + 5 0 *2 ns sck 3, sck4 scs3, scs40 to scs4 3 t cshd - 300 *2 t cshd + 5 0 *2 ns scs deselect time t cs di s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs 19 t csds - 50 *3 t csds +50 *3 ns scssck css e sck 1 to sck15, sck 18, sck19 s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs 19 - 3t cpp +30 - ns external shift clock mode output pin: c l = 5 0pf sckscs cs he +0 - ns scs deselect time t cs de s cs1 to scs3, scs40 to scs43, s cs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs 19 3t cpp +30 - ns d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 193 confidential parameter sym bol pin name con ditio n s value unit remarks min max scssot delay time t dse scs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, scs8 to scs15, scs18, scs19 sot1 , sot2, sot5 to sot15, sot18, sot 19 - - 40 ns external shift clock mode output pin: c l = 5 0pf scs3, scs40 to scs43 sot 3, sot 4 - 300 ns scssot delay time t dee s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs 19 sot1 to sot15, s ot1 8 , s ot19 +0 - ns sckscs clock switch time t scc sck 1 ,sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs 19 - 3t cpp - 1 0 3t cpp +50 ns internal shift clock mode round operation output pi n: c l = 5 0pf sck 3, sck4 scs3, scs40 to scs43 3t cpp - 30 0 3t cpp +50 ns *1: t cssu =scstr:cssu7 - 0 serial chip select timing operating clock *2: t cshd =scstr:cshd7 - 0 serial chip select timing operating clock *3: t csds =scstr:csds15 - 0 serial chip select ti ming operating clock regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at leas t five p eripheral bus clock cycles to be active again . please see the hardware manual for details of above - mention ed *1,*2, and *3. d a t a s h e et 194 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level "h" external shift clock mode sck input s ot (spi=0) s ot (spi=1) t csse scs input t cshe t csde t dse t dee when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level "h" internal shift clock mode , example of switching clock by round operation (x,y=0,1,2,3) scsy output s ck output scsx output t scc when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level "h" internal shift clock mode sck output s ot (spi=0) s ot (spi=1) t cssi scs output t cshi t csdi d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 195 confidential (4 - 1 - 6) bit setting : smr:md2=0, smr:md1=1, smr:md0=0 , when serial chip select is used : scscr:csen=1, serial clock output mark level "l " : smr,scsfr:scinv=1, serial chip select i nactive level "h" : scscr,scsfr:cslvl=1 (t a : - 40 c to + 1 2 5 c ,v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max scs sck cssi sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs1 9 - t cssu - 5 0 *1 t cssu +0 *1 ns internal shift clock mode output pin : c l = 5 0pf sck 3, sck 4 scs3, scs40 to scs43 t cssu - 5 0 *1 t cssu + 30 0 *1 ns sck scs cs hi sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs1 9 t cshd - 1 0 *2 t cshd + 5 0 *2 ns sck 3, sck 4 scs3, scs40 to scs43 t cshd - 30 0 *2 t cshd + 5 0 *2 ns scs deselect time t cs di s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs1 9 t csds - 50 *3 t csds +50 *3 ns scs sck css e sck 1 to sck11 s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs1 9 - 3t cpp +30 - ns external shift clock mode output pin: c l = 5 0pf sck scs cs he +0 - ns scs de select time t cs de s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs1 9 3t cpp +30 - ns d a t a s h e et 196 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential parameter sym bol pin name con ditio ns value unit remarks min max scs sot delay time t dse s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs1 9 sot1 , sot2, sot5 to sot15, s ot1 8 , s ot 1 9 - - 40 ns external shift clock mode output pin: c l = 5 0pf scs3, scs40 to scs43 sot 3, sot 4 - 300 ns scs sot delay time t dee s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs 73, s cs8 to scs15, scs 1 8 , scs1 9 sot1 to sot15, s ot1 8 , s ot 1 9 +0 - ns sck scs clock switch time t scc sck 1 , sck2, sck5 to sck15, sc k1 8 , sc k 1 9 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, scs 1 8 , scs1 9 - 3t cpp - 1 0 3t cpp +50 ns internal shift clock mode round operation output pin: c l = 5 0pf sck 3, sck 4 scs3, scs40 to scs43 3t cpp - 30 0 3t cpp +50 ns *1: t cssu =scstr:cssu7 - 0 serial chip select timing operating clock *2: t cshd =scstr:cshd7 - 0 serial chip select timing operating cl ock *3: t csds =scstr:csds15 - 0 serial chip select timing operating clock regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at least f ive p eripheral bus clock cycles to be active again . please see the hardware manual for details of above - mentioned *1,*2, and *3 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 197 confidential when serial ch ip select is used , serial clock output mark level " l " , serial chip select inactive level "h" internal shift clock mode sck output s ot (spi=0) s ot (spi=1) t cssi scs output t cshi t csdi when serial chip select is used , serial clock output mark level " l " , serial chip select inactive level "h" external shift clock mode sck input s ot (spi=0) s ot (spi=1) t csse scs input t cshe t csde t dse t dee when serial chip select is used , serial clock output mark level " l " , seria l chip select inactive level "h" internal shift clock mode , example of switching clock by round operation (x,y=0,1,2,3) scsy output s ck output scsx output t scc d a t a s h e et 198 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (4 - 1 - 7) bit setting : smr:md2=0, smr:md1=1, smr:md0=0 , when serial chip select is used : scscr:csen=1, serial clock output mark level "h " : smr,scsfr:scinv=0, serial chip select inactive level "l " : scscr,scsfr:cslvl=0 (t a : - 40 c to + 1 2 5 c ,v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max scs sck cssi sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, s cs18, scs19 - t cssu - 5 0 *1 t cssu +0 *1 ns internal shift clock mode output pin : c l = 5 0pf sck 3, sck 4 scs3, scs40 to scs43 t cssu - 5 0 * 1 t cssu + 30 0 *1 ns sck scs cs hi sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, s cs18, scs19 t cshd - 1 0 *2 t cshd + 5 0 *2 ns sck 3, sck 4 scs3, scs40 to scs43 t cshd - 30 0 *2 t cshd + 5 0 *2 ns scs des elect time t cs di s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, s cs18, scs19 t csds - 50 *3 t csds +50 *3 ns scs sck css e sck 1 to sck15, sck 18, sck19 s cs1 to scs3, scs40 to scs43, scs50 to scs53, sc s60 to scs63, scs70 to scs73, s cs8 to scs15, sc s18, scs19 - 3t cpp +30 - ns external shift clock mode output pin: c l = 5 0pf sck scs cs he +0 - ns scs deselect time t cs de s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, sc s18, scs19 3t cpp +30 - ns d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 199 confidential parameter sym bol pin name con ditio ns value unit remarks min max scs sot delay time t dse s cs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, sck 18, sck19 sot1 , sot2, sot5 to sot15, s ot18, sot19 - - 40 ns external shift clock mode output pin: c l = 5 0pf s cs3, scs40 to scs43 sot 3, sot 4 - 300 ns scs sot delay time t dee s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15 sck 18, sck19 sot1 to sot15, s ot18, sot19 +0 - ns sck scs clock swit ch time t scc sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, sc s18, scs19 - 3t cpp - 1 0 3t cpp +50 ns internal shift clock mode round operation output pin: c l = 5 0pf sck 3, sck4 s cs 3 , scs40 to scs43 3t cpp - 300 3t cpp +50 ns *1: t cssu =scstr:cssu7 - 0 serial chip select timing operating clock *2: t cshd =scstr:cshd7 - 0 serial chip select timing operating clock *3: t csds =scstr:csds15 - 0 serial chip select timing operating clock regardless of the d eselect time setting, once after the serial chip select pin becomes inactive, it will take at least five p eripheral bus clock cy cles to be active again . please see the hardware manual for details of above - mentioned *1,*2, and *3. d a t a s h e et 200 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level " l " internal shift clock mode sck output s ot (spi=0) s ot (spi=1) t cssi scs output t cshi t csdi when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level " l " external shift clock mode sck input s ot (spi=0) s ot (spi=1) t csse scs input t cshe t csde t dse t dee when serial chip select is used , serial clock output mark level " h " , serial chip select inactive level "l " internal shift clock mode , example of switching clock by round operation (x,y=0,1,2,3) scsy output s ck output scsx output t scc d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 201 confidential (4 - 1 - 8) bit setting : smr:md2=0, smr:md1=1, smr:md0=0 , when serial chip select is used : scscr:csen=1, serial clock output mark level "l " : smr,scsfr:scinv=1, serial chip select inactive level "l " : scscr,scsfr:cslvl=0 (t a : - 40 c to + 1 2 5 c ,v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter sym bol pin name con ditio ns value unit remarks min max scs sck cssi sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11, sc s18, scs19 - t cssu - 5 0 *1 t cssu +0 *1 ns internal shift clock mode output pin : c l = 5 0pf sck 3, sck 4 scs3, scs40 to scs43 t cssu - 5 0 *1 t cssu + 30 0 *1 ns sck scs cs hi sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11, sc s18, scs19 t cshd - 1 0 *2 t cshd + 5 0 *2 ns sck 3, sck 4 scs3, scs40 to scs4 3 t cshd - 30 0 *2 t cshd + 5 0 *2 ns scs deselect time t cs di s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs11, sc s18, scs19 t csds - 50 *3 t csds +50 *3 ns scs sck css e sck 1 to sck15, sck 18, sck19 s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, sc s18, scs19 - 3t cpp +30 - ns external shift clock mode output pin: c l = 5 0pf sck scs cs he +0 - ns scs deselect time t cs de s cs1 to scs3, scs40 to scs43, s cs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, sc s18, scs19 3t cpp +30 - ns d a t a s h e et 202 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential parameter sym bol pin name con ditio ns value unit remarks min max scs sot delay time t dse s cs1 , scs2, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, sc s18, scs19 sot1 , sot2, sot5 to sot15, s ot18, sot 19 - - 40 ns external shift clock mode output pin: c l = 5 0pf scs3, scs40 to scs43 sot 3, sot 4 - 30 0 ns scs sot delay time t dee s cs1 to scs3, scs40 to scs43, scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, sc s18, scs19 sot1 to sot15, s ot1 8, sot19 +0 - ns sck scs clock switch time t scc sck 1 , sck2, sck5 to sck15, sck 18, sck19 s cs1 , scs 2 , scs50 to scs53, scs60 to scs63, scs70 to scs73, s cs8 to scs15, sc s18, scs19 - 3t cpp - 1 0 3t cpp +50 ns internal shift clock mode round operation output p in: c l = 5 0pf sck 3, sck 4 scs3, scs40 to scs43 3t cpp - 30 0 3t cpp +50 ns *1: t cssu =scstr:cssu7 - 0 serial chip select timing operating clock *2: t cshd =scstr:cshd7 - 0 serial chip select timing operating clock *3: t csds =scstr:csds15 - 0 serial chip select t iming operating clock regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take at leas t five p eripheral bus clock cyc les to be active again . please see the hardware manual for details of above - mentio ned *1,*2, and *3. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 203 confidential when serial chip select is used , serial clock output mark level " l " , serial chip select inactive level "l " master mode sck output s ot (spi=0) s ot (spi=1) t cssi scs output t cshi t csdi when serial chip select is used , serial clock output mark level " l " , serial chip select inactive level " l " slave mode sck input s ot (sp i=0) s ot (spi=1) t csse scs input t cshe t csde t dse t dee when serial chip select is used , serial clock output mark level " l " , serial chip select inactive level "l " master mode , example of switching clock by round operation (x,y=0,1,2,3) scsy output s ck output scsx output t scc d a t a s h e et 204 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ( 4 - 2 ) uart ( asynchronous serial interface ) t iming bit setting : smr : md2=0, smr:md1= 0 , smr : md0=0 bit setting : smr : md2=0, smr:md1= 0 , smr : md0= 1 when external clock is selected (bgr:ext=1) (t a : - 40 c to + 1 2 5 c ,v cc =av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter symb ol pin name conditio ns value unit remarks min max serial clock "l" pulse width t slsh sc k0 to sck1 9 - t cp p +10 - ns output pin: c l = 5 0pf serial clock "h"pulse width t shs l t cp p +10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns (4 - 3) lin interface (v2.1)( asynchronous serial interface for lin (v2.1)) timing bit setting : smr : md2=0, smr:md1= 1 , smr : md0= 1 (t a : - 40 c to + 1 2 5 c ,v cc =av cc = 5.0v 10 % / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter symb ol pin name conditio ns value unit remarks min max serial clock "l" pulse width t slsh sc k0 to sck1 9 - t cp p +10 - ns output pin: c l = 5 0pf serial clock "h"pulse width t shsl t cp p +10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns when external clock is selected sck t shsl v il v ih v ih t r t slsh t f v il v ih v il when external clock is selected sck t shsl v il v ih v ih t r t slsh t f v il v ih v il d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 205 confidential ( 4 - 4 ) i 2 c t iming (t a : - 40 c to + 1 2 5 c ,v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v ) parameter sym bol pin name conditio ns standard mode high - speed mode * 3 unit rem arks min max min max scl clock frequency f scl sck 3 to sck 8, sck 11 to sck 19 c l =50pf r= (v p /i ol ) *1 0 100 0 400 khz repeat "start" condition hold time sda scl hdsta sot 3 to sot 8 , sot 11 to sot 19 (sda) , sck 3 to sck 8 , sck 11 to sck 19 (scl) 4 .0 C C low sck 3 to sck 8, sck 11 to sck 19 (scl) 4.7 C C high sck 3 to sck 8, sck 11 to sck 19 (scl) 4 .0 C C susta sck 3 to sck 8, sck 11 to sck 19 (scl) 4 .7 C C hddat sot 3 to sot 8 , sot 11 to sot 19 (sda) sck 3 to sck 8 , sck 11 to sck 19 (scl) 0 3.45 *2 0 0.9 *3 sudat sot 3 to sot 8 , sot 11 to sot 19 (sda) sck 3 to sck 8 , sck 11 to sck 19 (scl) 250 C C susto sot 3 to sot 8 , sot 11 to sot 19 (sda) sck 3 to sck 8 , sck 11 to sck 19 (scl) 4 .0 C C buf C C C s p C C cpp * 4 C cpp * 4 C l represent the pull - up resistance and load capacitance of the scl and sda output lines, respectively. vp shows that the power - supply voltage of the pull - up resistor and i ol shows the v ol guarantee current. * 2 : the maximum t hddat only has to be met if the device does not extend the " l " width (t low ) o f the scl signal . *3: a high - speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4: t cpp is the peripheral clock cycle time. adjust the clock of the bus in the surro unding to 8mhz or more when use i 2 c. d a t a s h e et 206 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? i 2 c timing sda scl t hdsta t low t hddat t sudat t high t susta t hdsta t sp t buf t susto d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 207 confidential ( 5 ) timer input timing (t a : - 40 c to + 1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tin0 to tin7 , icu0 to icu 11, frck0 to frck 10 , tioa 0 , tio a1, tio b0 , tio b1, ain0 to ain 3 , bin0 to bin 3 , zin0 to zin 3 C cp p C ? timer input timing ( 6 ) trigger input timing (t a : - 40 c to + 1 2 5 c , ,v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl int0 to int 23 , adtg 0 , adtg 1 , rx 0 to rx 5 C cp p C C ? trigg er input timing v ih v il t tiwl t tiwh v il tinx , icux , frck x , tioax,tiobx ain x ,bin x , zin x v ih v ih v il adtg t trgl t trgh v il intx rxx v ih d a t a s h e et 208 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ( 7 ) nmi input timing (t a : - 40 c to + 1 2 5 c , v cc = av cc = 5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v ) parameter symbol pin name conditions value unit remarks min max input pulse width t nmil nmix C c p p C ? nmix input timing v ih 5 nmix t nmil v ih 5 v il 5 v il 5 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 209 confidential ( 8 ) low voltage detection (external low - voltage detection) (t a : - 40 c to + 1 2 5 c , v ss =av ss =0.0v) parameter symbol pin name conditi ons value unit remarks min typ max power supply voltage range v dp5 v cc - 2. 7 - 5.5 v detection voltage v d l * 1 - 8% 2.8 +8% v when power - supply voltage falls and detection level is set initially hysteresis width v hys - - 0.1 - v when power - supply voltage rises low voltage detection time td - - - 3 0 s power supply v oltage regulation - vcc - - 2 - 2 v/ms * 2 * 1 : if the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection voltage range. * 2 : p lease suppress the change of the power supply within the range of the power - supply voltage regulation to do a low voltage detection by detecting voltage ( v d l ). ( 9 ) low voltage detection (internal low - voltage detection) (t a : - 40 c to + 1 2 5 c , v ss =av ss =0.0v ) parameter symbol pin name con ditio ns value unit remarks min typ max power supply voltage range v rd p5 - - 0.6 - 1.4 v detection voltage v rd l * 0.8 0 . 9 1.0 v when power - supply voltage fall s hysteresis width v rh ys - - 0.1 - v when power - supply voltage rises low voltage detection time - - - - 3 0 s *: if the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release after the power supply voltage has exceeded the detection volt age range. d a t a s h e et 210 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (10) external bus i/f (synchronous mode) timing (t a : - 40 c to + 105 c , v cc =av cc =5.0v10% / v cc = av cc = 3.3 v 0.3v , v ss =av ss =0.0v) ( external load capacitance 50pf) parameter symbol pin name value unit remarks min max cycle time t cyc sysclk 25 - ns v cc = 5.0v 10% *1 31.25 v cc = 3.3v 0.3 v asx delay time t chasl , t chash sysclk , asx 0.5 18 ns cs0x to cs3x delay time t chcsl , t chcsh sysclk , cs0x to cs3x 0.5 18 ns a00 to a21 delay time t chav , t chax sysclk , a00 to a21 0.5 18 ns rdx delay time t chrl , t chrh sysclk , rdx 0.5 18 ns rdx minimum pulse t rlrh rdx t cyc 2 - 20 - ns rwt=1, set rwt to 1 or more. * 2 data setup rdx dsrh rdx , d16 to d31 18 + t cyc - ns same as above rdx rhdh 0 - ns wrnx delay time t chwl , t chwh sysclk , wr0x, wr1x 0.5 18 ns wrnx minimum pulse t wlwh wr0x, wr1x t cyc - 10 - ns wwt=0 *2 sysclk chdv sysclk , d 16 to d31 0.5 18 ns sysclk chdx - 18 ns set wrcs to 1 or more. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 211 confidential parameter symbol pin name value unit remarks min max sysclk address output time t chmav sysclk , d16 to d31 0.5 18 ns sysclk address hold time t chmax - 18 ns in multiplex mode, set as follows: ? s et cswr and csrd to 2 or more. ? ascy must satisfy the following conditions because of setting adcy > ascy and protocol violation prevention. adcy + 1 acs + csrd adcy + 1 acs + cswr ascy + 1 acs + csrd ascy + 1 acs + cswr see hardware manual for det ails. * 1 : please use it with external load capacity 12pf or less for v cc e =3.3v0.3v (40mhz operation). * 2 : if the bus is expanded by automatic wait insertion or rdy input, add time (t cyc the number of expanded cycles) to the rated value. d a t a s h e et 212 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential external bus i/f (synchronous mode, read operation, and multiplex mode) timing external bus i/f (synchronous mode, read operation, and split mode) timing cs0x to cs3x cs0x to cs3x cs0x to cs3x d16 to d31 d16 to d31 a00 to a21 valid address read data t1 t2 t3 sysclk asx cs0x~cs3x rdx d16~d31 tchasl tchash tchcsl tchcsh tchrl tchrh tchmax trhdh t cyc tdsrh trlrh t4 csrd=2 adcy=1 rwt=1 tchmav ascy=0 acs=0 rdcs=0 valid address read data t1 t2 t3 sysclk asx cs0x~cs3x rdx a00~a21 d16~d31 tchcsh tchrl tchrh tchav tchax trhdh tdsrh trlrh t4 csrd=0 rwt=1 tchcsl t cyc acs=0 rdcs=0 tchasl tchash ascy=0 d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 213 confidential external bus i/f (synchronous mode, write operation, and multiplex mode) timing external bus i/f (synchronous mode, write operation, an d split mode) timing cs0x to cs3x wr0x to wr1x d16 to d31 cs0x to cs3x wr0x to wr1x d16 to d31 a00 to a21 valid address write data t1 t2 t3 sysclk asx cs0x~cs3x wr0x~wr1x d16~d31 tchasl tchash t cyc tchcsl tchcsh tchwl tchwh tchdv tchdx twlwh adcy=1 cswr=2 t4 wrcs=1 tchmav wwt=0 acs=0 ascy=0 valid address write data t1 t2 t3 sysclk asx cs0x~cs3x wr0x~wr1x a00~a21 d16~d31 tchcsh tchwl tchwh tchav tchax tchdx twlwh cswr=0 t4 wrcs=1 tchdv tchasl t cyc tchash ascy=0 tchcsl acs=0 wwt=0 d a t a s h e et 214 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (11) external bus i/f ( a synchronous mode) timing (t a : - 40 c to + 105 c ,v cc =av cc =5.0v10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) ( external load capacitance 50p f) parameter symbol pin name value unit remarks min max cycle time t cyc sysclk 25 - ns v cc = 5.0v 10% *1 31.25 v cc = 3.3v 0.3 v address setup rdx asrh rdx , a00 to a21 2 t cyc - 12 2 t cyc + 12 ns rwt=1 , set rwt to 1 or more. * 2 rdx rhah t cyc - 12 t cyc + 12 ns set rdcs to 1 or more . data setup rdx dsrh rdx , d16 to d31 18 + t cyc - ns rwt=1, set rwt to 1 or more. rdx rhdh 0 - ns address setup wrnx aswh wr0x to wr1x , a00 to a21 t cyc - 12 t cyc + 12 ns wwt=0 * 2 wrnx whah t cyc - 12 t cyc + 12 ns set wrcs to 1 or more. data setup wrnx dswh wr0x to wr1x , d16 to d31 t cyc - 16 t cyc + 16 ns wwt=0 * 2 wrnx whdh t cyc - 16 t cyc + 16 ns set wrcs to 1 or more. address setu p asxtime masash asx , d16 to d31 t cyc - 16 t cyc + 16 ns ascy=0 asx mashah t cyc - 16 t cyc + 16 ns in multiplex mode, set as follows: ? ? cc e =3.3v0.3v (40mhz operation). * 2 : if the bus is expanded by automatic wait insertion or rdy input, add time (t cyc the number of expanded cycles) to the rated value. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 215 confidential external bus i/f (asynchronous mode, read operation, and multiplex mode) timing external bus i/f (asynchronous mode, read operation, and split mode) timing cs0x to cs3x d16 to d31 a00 to a21 cs0x to cs3x d16 to d31 valid address t1 t2 t3 sysclk asx cs0x~cs3x rdx d16~d31 csrd=2 adcy=1 t4 read data rwt=1 trhdh tdsrh t5 rdcs=1 tmasash tmashah acs=0 ascy=0 t cyc t1 t2 t3 sysclk asx cs0x~cs3x rdx a00~a21 d16~d31 csrd=0 t4 read data valid address rwt=1 trhdh tdsrh t5 rdcs=1 tasrh trhah acs=0 ascy=0 t cyc d a t a s h e et 216 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential external bus i/f (asynchronous mode, write operation, and m ultiplex mode) timing external bus i/f (asynchronous mode, write operation, and split mode) timing cs0x to cs3x d16 to d31 cs0x to cs3x d16 to d31 a00 to a21 wr0x to wr1x cs0x to cs3x wr0x to wr1x valid address write data t1 t2 t3 sysclk asx cs0x~cs3x wr0x~wr1x d16~d31 wrcs=1 adcy=1 t4 cswr=2 tmasash tmashah tdswh twhdh ascy=0 acs=0 wwt=0 t cyc valid address write data t1 t2 t3 sysclk asx cs0x~cs3x wr0x~wr1x a00~a21 d16~d31 wrcs=1 t4 cswr=0 taswh twhah tdswh twhdh ascy=0 acs=0 wwt=0 t cyc d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 217 confidential (12) external bus i/f (ready) timing (t a : - 40 c to + 105 c ,v cc =av cc =5. 0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) ( external load capacitance 50pf) parameter symbol pin name value unit remarks min max cycle time t cyc sysclk 50 - ns if using rdy, set sysclk to 20 mhz or less. rdy setup time sysclk rdys sysclk , rdy 28 - ns sysclk rdyh sysclk , rdy 0 - ns external bus i/f (ready) timing auto wait cycle added cycle by rdy t3 t4 t5 sysclk asx cs0x~cs3x rdx rdy trdys trdyh t6 rwt=2 csrd=2 ascy=0 acs=0 rdcs=0 t1 t2 t cyc d a t a s h e et 218 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential 5. a/d converter (1) 12 - bit a/d converter electrical characteristics (t a : - 40 c to + 1 2 5 c , v cc =av cc =5.0v 10% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v ) parameter sym bol pin name value unit remarks min typ max resolution - - - - 12 bit total error - - - - 12 lsb l inearity error - - - - 4.0 lsb differential linearity error - - - - 1.9 lsb zero transition voltage v ot an0 to an 63 av rl - 11.5 lsb - av rl + 12.5 lsb v 1lsb= (v fst - v ot )/ 4094 full - scale transition voltage v fst an0 to an 63 av rh - 13 . 5 lsb - av rh+ 10 . 5 lsb v sampling time t smp - 0.7 - - s *1 compare time t cmp - 0.7 - - s * 1 a/d conversion time t cnv - 1.4 - - s * 1 analog port input current i ain an0 to an 63 - 1 . 0 - + 1 . 0 a v avss ain avcc analog input voltage v ain an0 to an 63 av rl - av rh v reference voltage avr h av rh 3.0 - 5.5 v avr l avss / avrl - 0.0 - v power supply current i a avcc * 3 - 0.47 0 .63 m a per unit t a : +105 c - 0.47 0.7 m a per unit t a : +125 c i ah - - 2.5 a *2 i r avrh - 1 1.96 m a per unit i rh - - 1.6 a *2 variation between channels - an0 to an 63 - - 4 lsb *1 : time for each channel. *2 : power supply current (v cc = av c c = 5.0 v) is specified if a/d converter is not operating and cpu is stopped. *3: the power supply current described only current value on a/d converter. the total avcc current value must be calculated the power supply current for a/d converter and d/a co nverter. ( n ote) please use the clock of 0.5 mhz - 20 mhz for the output clock of a/d converter to guarantee accuracy. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 219 confidential (2) definition of a/d converter terms resolution : analog variation that is recognized by an a/d converter. linearity error : deviation of the actual conversion characteristics from a straight line that connects the zero transition point (" 00 00 0000 000 0" " 1111 1110" " linearity error of digital output n = v nt - {1lsb (n - 1) + v ot } [lsb] 1lsb differential linearity error of digital output n = v (n + 1) t - v nt - 1 lsb [lsb] 1lsb 1lsb = v fst - v ot [v] 4094 v ot : voltage at which the digital output changes from 000 h to 001 h . v fst : voltage at which the digital output changes from f fe h to f ff h . d a t a s h e et 220 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential (3) notes on using a/d converter d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 221 confidential 6. flash memory (1) electrical characteristics parameter value unit remarks min typ max sector erase time C 200 800 m s 8 kbyte s sector * 1 , e xcluding internal pre programming time C 300 1100 m s 8 kbyte s sector * 1 , in cluding internal pre programming time C 400 2000 m s 64 kbyte s sector * 1 , excluding internal preprog ramming time C 700 3700 m s 64 kbyte s sector * 1 , in cluding internal preprog ramming time 8 - bit writing time C 9 288 s exclusive of overhead time at system level * 1 16 - bit writing time C 12 384 s exclusive of overhead time at system le vel * 1 ecc writing time C 9 288 s exclusive of overhead time at system level * 1 erase cycle * 2 / data retain time 1 , 000 cycles / 20 years , 10 , 000 cycles / 10 years , 100 , 000 cycles / 5 years C C C average t a =+85 c * 3 * 1: the guaranteed value for erasure up to 100,000 cycle s . * 2: number of erase cycles for each sector. * 3: this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85c). (2 ) notes while the flash memory is written or erased , shutdown of the external power (vcc) is prohibited. in the application system where vcc might be shut down while writing or erasing , be sure to turn the power off by using an external voltage detection function . to put it concretely, af ter the external power supply voltage falls below the detection voltage (v dl * ), hold vcc at 2.7v or more within the duration calculated by the following expression: td * [ s ] + (period of pclk [ s ] 257) + 50 [ s ] *: see 4.ac characteristics ( 8 ) low - voltage detection (external low - voltage detection) d a t a s h e et 222 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential 7. d/a converter (t a : - 40 c to + 1 2 5 c ,v cc =av cc =5.0v 1 0% / v cc = av cc = 3 . 3 v 0.3v ,v ss =av ss =0.0v) parameter symbol pin name condition value unit remarks min typ max resolution - - C C C 8 b it differential linearity error - - C C C 3.0 lsb conversion time - - C 0.47 0.58 0.69 s c l =20 C 2.37 2.90 3.43 s c l =100 output impedance ro da0, da1 C 3.1 3.8 4.5 k power supply current * 1 ia av cc C C 475 580 a e ach channel iah av cc C C C 7.5 a when powerdown e ach channel *1: the power supply current described only current value on d/a converter. the total avcc current value must be calculated the power supp ly current for d/a converter and a/d converter. d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 223 confidential example characteristic s this characteristic is an actual value of the arbitrary sample. it is not the guaranteed value. ? mb91f528 10.00 100.00 -50 0 50 100 150 i cc 5 [ma] t a [oc] normal operation pll clock (80mhz) pll clock(64mhz) pll clock (48mhz) (v cc = 5.5v) pll clock (128mhz) 10.00 100.00 -50 0 50 100 150 i cc s5/ i cc bs5 [ma] t a [oc] sleep mode cpu sleep(80mhz) bus sleep (80mhz) (v cc = 5.5v) d a t a s h e et 224 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? mb91f528 0.001 0.010 0.100 1.000 10.000 -50 0 50 100 150 i cc t5 [ma] t a [oc] watch mode main osc (4mhz) rc clock (50khz) (v cc = 5.5v) (v cc = 5.5v) sub osc (32khz) 0.001 0.010 0.100 1.000 10.000 -50 0 50 100 150 i cc h5 [ma] t a [oc] stop mode (v cc = 5.5v) d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 225 confidential ? mb91f528 0.01 0.10 1.00 10.00 100.00 1000.00 -50 0 50 100 150 i cc t52 [ a ] t a [oc] watch mode(power off) main osc (4mhz) rc clock (50khz) (v cc = 5.5v) (v cc = 5.5v) sub osc (32khz) 0.01 0.10 1.00 10.00 100.00 1000.00 -50 0 50 100 150 i cc h52 [ a ] t a [oc] stop mode(power off) (v cc = 5.5v) d a t a s h e e t 226 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential ? ordering information part number sub clock csv initial value lvd initial value package * 1 MB91F528Y w cpb yes on on bga ? 416 pin, p lastic ( bga - 416p - m05 ) MB91F528Yycpb off MB91F528Yjcpb off on MB91F528Ylcpb off mb91f527y w cpb on on mb91f527yycpb off mb91f527yjcpb off on mb91f527ylcpb off MB91F528Y s cpb none on on MB91F528Yucpb off MB91F528Yhcpb off on MB91F528Ykcpb off mb91f527y s cpb on on mb91f527yucpb off mb91f527yhcpb off on mb91f527ykcpb off mb91f528m w cpmc yes on on lqfp ? 208 pin, p lastic (fpt - 208p - m06 ) mb91f528mycpmc off mb91f528mjcpmc off on mb91f528mlcpmc off mb91f527m w cpmc on on mb91f527mycpmc off mb91f527mjcpmc off on mb91f527mlcpmc off mb91f528m s cpmc none on on mb91f52 8mucpmc off mb91f528mhcpmc off on mb91f528mkcpmc off mb91f527m s cpmc on on mb91f527mucpmc off mb91f527mhcpmc off on mb91f527mkcpmc off d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 227 confidential part number sub clock csv initial value lvd initial value package * 1 mb91f528u w cpmc yes on on lqfp ? 176 pin, p lastic (fpt - 1 76p - m07) mb91f528uycpmc off mb91 f528ujcpmc off on mb91f528ulcpmc off mb91f527u w cpmc on on mb91f527uycpmc off mb91f527ujcpmc off on mb91f527ulcpmc off mb91f528u s cpmc none on on mb91f528uucpmc off mb91f528uhcpmc off on mb91f528ukcpmc off mb91f527u s cpmc on on mb91f527uucpmc off mb91f527uhcpmc off on mb91f527ukcpmc off mb91f528r w cpmc yes on on lqfp ? 144 pin, ( lead pitch 0.5mm) p lastic (fpt - 144p - m08) mb91f528rycpmc off mb91f528rjcpmc off on mb91f528rlcpmc off mb91f527r w cpmc on on mb91f527rycpmc off mb91f527rjcpmc off on mb91f527rlcpmc off mb91f528r s cpmc none on on mb91f528rucpmc off mb91f528rhcpmc off on mb91f528rkcpmc off mb91f527r s cpmc on on mb91f527rucpmc off mb91f527rhcpmc off on mb91f527r kcpmc off d a t a s h e e t 228 mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e, march 28 , 2014 confidential part number sub clock csv initial value lvd initial value package * 1 mb91f528r w cpmc1 yes on on lqfp ? 144 pin, ( lead pitch 0.4mm ) p lastic (fpt - 144p - m 12 ) mb91f528rycpmc1 off mb91f528rjcpmc1 off on mb91f528rlcpmc1 off mb91f527r w cpmc1 on on mb91f527rycpmc1 off mb91f527rjcpmc1 off on mb9 1f527rlcpmc1 off mb91f528r s cpmc1 none on on mb91f528rucpmc1 off mb91f528rhcpmc1 off on mb91f528rkcpmc1 off mb91f527r s cpmc1 on on mb91f527rucpmc1 off mb91f527rhcpmc1 off on mb91f527rkcpmc1 off mb91f528m w ceq yes on on teq fp ? 208 pin, p lastic (fpt - 208p - m 36 ) mb91f528myceq off mb91f528mjceq off on mb91f528mlceq off mb91f527m w ceq on on mb91f527myceq off mb91f527mjceq off on mb91f527mlceq off mb91f528m s ceq none on on mb91f528muceq off mb91f528mhc eq off on mb91f528mkceq off mb91f527m s ceq on on mb91f527muceq off mb91f527mhceq off on mb91f527mkceq off d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 229 confidential part number sub clock csv initial value lvd initial value package * 1 mb91f528u w ceq yes on on teqfp ? 176 pin, p lastic (fpt - 1 76p - m 18 ) mb91f528uyceq off mb91f528ujceq off on mb91f528ulceq off mb91f527u w ceq on on mb91f527uyceq off mb91f527ujceq off on mb91f527ulceq off mb91f528u s ceq none on on mb91f528uuceq off mb91f528uhceq off on mb91f528ukceq off mb91f527u s ceq on on mb91f527uuceq off mb91f527uhceq of f on mb91f527ukceq off mb91f528r w ceq yes on on teqfp ? 144 pin, p lastic ( planning * 2 ) mb91f528ryceq off mb91f528rjceq off on mb91f528rlceq off mb91f527r w ceq on on mb91f527ryceq off mb91f527rjceq off on mb91f527rlceq off mb91f528r s ceq none on on mb91f528ruceq off mb91f528rhceq off on mb91f528rkceq off mb91f527r s ceq on on mb91f527ruceq off mb91f527rhceq off on mb91f527rkceq off * 1 : for details of the package , see " ? package dimensions ". * 2 : teqfp - 144pin is planning. please contact sales representatives about details. datasheet ? package dimensions 144-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 20.0 20.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 1.20 g code (reference ) p-lfqfp144-20 20-0.5 0 144-pin plastic lqfp (fpt -144p-m08) (fpt-144p-m08) details of "a" part 0.25(.010) (stand off) (.004.004) 0.100.10 (.024.006) 0.600.15 (.020.008) 0.500.20 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ~8 0.50(.020) "a" 0.08(.003) 0.1450.055 (.006.002) lead no. 1 36 index 37 72 73 108 109 144 0.220.05 (.009.002) m 0.08(.003) 22.000.20(.866.008)sq (mounting height) * 20.000.10(.787.004)sq dimensions in mm (inches). note: the values in parentheses are reference values. note 1) *:values do not include resin protrusion. resin protrusion is +0.25(.010)max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. c 2003-2010 fujitsu semiconductor limited f144019s-c-4-8 please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ 230 mb9 1f528_ ds70 5 - 00016- 1 v 0 - e, march 28 , 2014 confidential datasheet 144-pin plastic lqfp lead pitch 0.40 mm pa ck age width pa ck age length 16.0 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max we ight 0.88 g code (reference ) p-lfqfp144-16 16-0.4 0 144-pin plastic lqfp (fpt -144p-m12) (fpt-144p-m12) c 2003-2010 fujitsu semiconductor limited f144024s-c-3-5 .059 ? .004 +.008 ? 0.10 +0.20 1.50 details of "a" part 0~8 (mounting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0.08(.003) 0.145 ? 0.03 +.002 ? .001 .006 +0.05 "a" .007.001 0.180.035 m 0.07(.003) 36 37 1 lead no. 0.40(.016) index 144 109 108 18.000.20(.709.008)sq sq 16.00 73 72 * .630 ? .004 +.016 ? 0.10 +0.40 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions include resin protrusion. resin protrusion is +0.25(.010)max(each side). note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ march 28 , 2014, mb9 1f528_ ds70 5 - 00016- 1 v 0 - e 231 confidential datasheet 176-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 24.0 24.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x code (reference ) p-lqfp-0176-2424-0.5 0 176-pin plastic lqfp (fpt -176p-m07) (fpt-176p-m07) c details of "a" part 0~8 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) (stand off) (.004.004) 0.100.10 1.50 +0.20 ?0.10 +.008 ?.004 .059 (mounting height) 0.08(.003) (.006.002) 0.1450.055 "a" index 1 lead no. 44 45 88 89 132 133 176 0.50(.020) 0.220.05 (.009.002) m 0.08(.003) *24.000.10(.945.004)sq 26.000.20(1.024.008)sq dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : values do not include resin protrusion. resin protrusion is +0.25(.010)max(each side). note 2) pins width and pins thickness include plating thickness note 3) pins width do not include tie bar cutting remainder. 2004-2010 fujitsu semiconductor limited f176013s-c-1-3 p lease confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ 232 mb9 1f528_ ds70 5 - 00016- 1 v 0 - e, march 28 , 2014 confidential datasheet 208-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 28.0 28.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 2.55 g code (reference ) p-lfqfp208-28 28-0.5 0 208-pin plastic lqfp (fpt -208p-m06) (fpt-208p-m06) c 2003-2010 fujitsu semiconductor limited f208027s-c-3-5 details of "a" part 0.25(.010) (stand off) (.004.002) 0.100.05 (.024.006) 0.600.15 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ~8 "a" 0.08(.003) (.006.002) 0.1450.055 index 1 lead no. 52 53 104 105 156 157 208 0.50(.020) 0.08(.003) m (.009.002) 0.220.05 28.000.10(1.102.004)sq 30.000.20(1.181.008)sq (mounting height) * dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ march 28 , 2014, mb9 1f528_ ds70 5 - 00016- 1 v 0 - e 233 confidential datasheet 176-pin plastic teqfp lead pitch 0.50 mm pa ck age width package lengt h 24.00 mm 24.00 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max. we ight 1.86 g code (reference ) p-teqfp176-24 24-0.5 0 176-pin plastic teqfp (fpt-176p-m18) (fpt-176p-m18) 0.220.05 (.009.002) * 24.000.10(.945.004) sq 26.000.20(1.024.008) sq 0.1450.055 1.50 (.059 ) 0 ? ~8 ? 0.25(.010) 0.100.10 (.004.004) index details of "a" part (.020) 0.600.15 (.024.006) "a" 0.50 1 44 88 45 132 89 176 133 (.006.002) m 0.08(.003) 0.08(.003) (9.26(.365) sq) c 2013 fujitsu semiconductor limited hmbf176-18sc-1-1 0.500.20 (.020.008) (8.06(.317) sq) (mounting height) (stand off) +0.20 -0.10 +.008 -.004 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest p ackage dimension by following url. http://edevice.fujitsu.com/package/ en - search/ 234 mb9 1f528_ ds70 5 - 00016- 1 v 0 - e, march 28 , 2014 confidential datasheet 208-pin plastic teqfp lead pitch 0.50 mm pa ck age width package lengt h 28.00 mm 28.00 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm max. we ight 2.55 g code (reference ) p-teqfp208-28 28-0.5 0 208-pin plastic teqfp (fpt-208p-m36) (fpt-208p-m36) 0.220.05 (.009.002) * 28.000.10(1.142.004) sq 30.000.20(1.181.008) sq 0.1450.055 1.50 (.059 ) 0 ? ~8 ? 0.25(.010) 0.100.10 (.004.004) index details of "a" part (.020) 0.600.15 (.024.006) "a" 0.50 1 52 104 53 156 105 208 157 (.006.002) m 0.08(.003) 0.08(.003) (9.26(.365) sq) c 2013 fujitsu semiconductor limited hmbf208-36sc-1-1 (8.06(.317) sq) (mounting height) (stand off) +0.20 -0.10 +.008 -.004 dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/ en - search/ march 28 , 2014, mb9 1f528_ ds70 5 - 00016- 1 v 0 - e 235 confidential datasheet 416-pin plastic pbga lead pitch 1.00 mm pa ck age width pa ck age length 27.00 mm 27.00 mm lead shape ball sealing method plastic mold mounting height 2.37 mm max 416-pin plastic pbga (bga-416p-m05 ) (bga-416p-m05) 2006-2010 fujitsu semiconductor limited bga416005sc-2-4 24.000.10(.945.004) 27.00(1.063) 27.00 24.000.10 (1.063) (.945.004) 0.20(.008) (4x) 25.00(.984) 1.00(.039) 1.00(.039) ref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1.00(.039) 1.00(.039) ref 25.00 (.984) ?0.600.10(.024.004) a c c m 0.10(.004) 0.25(.010) m b b a b ac ab aa a c d e f g h j k l m n p r t u v w y ad ae af 0.500.10 (.020.004) 2.37(.093) max. c 0.15(.006) c index c dimensions in mm (inches). note: the values in parentheses are reference values. please confirm the latest package dimension by foll owing url. http://edevice.fujitsu.com/package/ en - search/ 236 mb9 1f528_ ds70 5 - 00016- 1 v 0 - e, march 28 , 2014 confidential d a t a s h e e t march 28 , 2014 , mb9 1f528_ ds70 5 - 000 16 - 1 v 0 - e 237 confidential major changes page section change results revision 1.0 - - initial release d a t a s h e e t 238 mb91f528_ds705- 00016 -1v0-e, march 28 , 2014 confidential colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including without limi tation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffi c control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above - mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those prod ucts. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any pro duct without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non - infringement of third - party rights, or any other warranty, express, implied, or statutory. spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2014 spansion inc. all rights reserved. spansion ? , the spansion logo, mirror bit ? , mirrorbit ? eclipse tm , ornand tm and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners. |
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